HDLBits刷题（电路-顺序逻辑-计数器）

Four-bit binary counter

module top_module (
    input clk,
    input reset,      
    output [3:0] q);
    always @(posedge clk )begin
        if(reset) q<=4'b0;
        else q=q+4'b0001;
    end
endmodule

Dacade counter

module top_module (
    input clk,
    input reset,       
    output [3:0] q);
     always @(posedge clk )begin
         if(reset) q<=4'd0;
        else begin
            if(q==4'd9) 4'd0;
            else q<=q+4'd1;
    end
endmodule

Dacade counter again

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    always @(posedge clk )begin
        if(reset) q<=4'd1;
        else begin
            if(q==4'd10) q<=4'd1;
            else q<=q+4'd1;end
    end
endmodule

slow decade counter 

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    always @(posedge clk )begin
        if(reset) q<=4'd0;
        else begin
            if(slowena==1'b1) 
                if(q==4'd9) q<=4'd0;else q<=q+4'd1;
            else q<=q;end
    end
endmodule

counter 1-12

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); 
	assign c_enable=enable;
    assign c_load=(reset||((Q==4'd12)&&(enable==4'd1)));
    assign c_d=c_load?4'd1:4'd0;
    count4 the_counter (clk, c_enable, c_load, c_d ,Q );
endmodule

couter 1000

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); 
	wire [3:0] one,ten,hundred;
    assign c_enable = {one == 4'd9&&ten == 4'd9,one == 4'd9,1'b1};
    assign OneHertz = one == 4'd9&&ten == 4'd9&&hundred == 4'd9;
    bcdcount counter0 (clk, reset, c_enable[0],one);
    bcdcount counter1 (clk, reset, c_enable[1],ten);
    bcdcount counter2 (clk, reset, c_enable[2],hundred);
endmodule

4 digit decimal counter

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
	always @(posedge clk )begin
        if(reset) begin q[3:0]<=4'd0;ena[1]<=1'd0 ;end
        else if(q[3:0]==4'd9) begin q[3:0]=4'd0;ena[1]<=1'd0 ;end
        else if(q[3:0]==4'd8) begin q[3:0]<=q[3:0]+4'd1;ena[1]<=1'd1 ;end
        else  begin q[3:0]<=q[3:0]+4'd1 ;ena[1]<=1'd0 ;end
    end
    always @(posedge clk )begin
        if(reset) begin q[7:4]<=4'd0;ena[2]<=1'd0 ;end
        else if(ena[1]==1'd1&&q[7:4]==4'd9) begin q[7:4]=4'd0;ena[2]<=1'd0 ;end
        else if(q[3:0]==4'd8&&q[7:4]==4'd9) begin q[7:4]<=q[7:4];ena[2]<=1'd1 ;end
        else if(ena[1]==1'd1) begin q[7:4]<=q[7:4]+4'd1 ;ena[2]<=1'd0 ;end
        else  begin q[7:4]<=q[7:4] ;ena[2]<=1'd0 ;end
    end
    always @(posedge clk )begin
        if(reset) begin q[11:8]<=4'd0;ena[3]<=1'd0 ;end
        else if(ena[1]==1'd1&&ena[2]==1'd1&&q[11:8]==4'd9) begin q[11:8]=4'd0;ena[3]<=1'd0 ;end
        else if(q[7:4]==4'd9&&q[3:0]==4'd8&&q[11:8]==4'd9) begin q[11:8]<=q[11:8];ena[3]<=1'd1 ;end
        else if(ena[1]==1'd1&&ena[2]==1'd1) begin q[11:8]<=q[11:8]+4'd1 ;ena[3]<=1'd0 ;end
        else  begin q[11:8]<=q[11:8] ;ena[3]<=1'd0 ;end
    end
    always @(posedge clk )begin
        if(reset) begin q[15:12]<=4'd0;end
        else if(ena[1]==1'd1&&ena[2]==1'd1&&ena[3]==1'd1&&q[15:12]==4'd9) begin q[15:12]=4'd0;end
        else if(ena[1]==1'd1&&ena[2]==1'd1&&ena[3]==1'd1) q[15:12]<=q[15:12]+4'd1 ;
        else q[15:12]<=q[15:12] ;
    end
endmodule

count clock

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output reg [7:0] hh,
    output reg [7:0] mm,
    output reg [7:0] ss); 
	always @(posedge clk )begin
        if(reset) begin ss<=8'h00;;end
    	else if(ss==8'h59&&ena==1'b1) ss<=8'h00;
        else if(ss[3:0]==4'h9&&ena==1'b1) begin ss[3:0]<=4'h0; ss[7:4]<=ss[7:4]+4'h1;end
        else if(ena==1'b1) ss[3:0]<=ss[3:0]+4'h1;
        else ss<=ss;
	end
    always @(posedge clk )begin
    	if(reset) begin mm<=8'h00;end
        else if(ss==8'h59&&mm==8'h59&&ena==1'b1) mm<=8'h00;
        else if(ss==8'h59&&mm[3:0]==4'h9&&ena==1'b1) begin mm[3:0]<=4'h0; mm[7:4]<=mm[7:4]+4'h1;end
        else if (ss==8'h59&&ena==1'b1) mm[3:0]<=mm[3:0]+4'h1;
        else mm<=mm;
	end
    always @(posedge clk )begin
        if(reset) begin hh<=8'h12; end
        else if(ss==8'h59&&mm==8'h59&&hh==8'h12&&ena==1'b1) hh<=8'h01;
        else if(ss==8'h59&&mm==8'h59&&hh[3:0]==4'h9&&ena==1'b1) begin hh[3:0]<=4'h0; hh[7:4]<=hh[7:4]+4'h1;end
        else if (ss==8'h59&&mm==8'h59&&ena==1'b1) hh[3:0]<=hh[3:0]+4'h1;
        else hh<=hh;
	end
    always @(posedge clk )begin
        if(reset) begin pm<=1'b0; end
        else if(ss==8'h59&&mm==8'h59&&hh==8'h11&&ena==1'b1) pm<=~pm;
        else pm<=pm;
	end
endmodule