FPGA入门学习笔记（十七）Vivado实现DDS结构

基本原理

仿真波形

设计文件程序

`timescale 1ns / 1ns
module DDS_Module(
        Clk,
        Reset_N,
        Fword,
        Pword,
        Data
    );
    input Clk;
    input Reset_N;
    input [31:0]Fword;
    input [11:0]Pword;
    output [13:0]Data;
    
    //频率控制字的同步寄存器
    reg [31:0]Fword_r;
    always@(posedge Clk)
        Fword_r <= Fword;
        
    //相位控制字的同步寄存器
    reg [11:0]Pword_r;
    always@(posedge Clk)
        Pword_r <= Pword;
        
    reg [31:0]Freq_ACC;
    always@(posedge Clk or negedge Reset_N)
    if(!Reset_N)
        Freq_ACC <= 0;
    else
        Freq_ACC <= Fword_r + Freq_ACC;
    
    //波形数据表的地址
    //查ROM表输出序列
    wire [11:0]Rom_Addr;
    assign Rom_Addr = Freq_ACC[31:20] + Pword_r;
        
    blk_mem_gen_0 blk_mem_gen_0 (
      .clka(Clk),
      .addra(Rom_Addr),
      .douta(Data)
    );    
endmodule

仿真文件程序

`timescale 1ns / 1ns

module DDS_Module_tb();
    reg Clk;
    reg Reset_N;
    reg [31:0]FwordA,FwordB;
    reg [11:0]PwordA,PwordB;
    wire [13:0]DataA,DataB;
    DDS_Module DDS_ModuleA(
        Clk,
        Reset_N,
        FwordA,
        PwordA,
        DataA
    );
    DDS_Module DDS_ModuleB(
        Clk,
        Reset_N,
        FwordB,
        PwordB,
        DataB
    );
    initial Clk = 1;
    always #10 Clk = !Clk;
    initial begin
        Reset_N = 0;
        FwordA = 65536*32;
        PwordA = 0;
        FwordB = 65536*32;
        PwordB = 1024;
        #201;
        Reset_N = 1;
        #2000000;
        FwordA = 65536*32;
        PwordA = 0;
        FwordB = 65536*32;
        PwordB = 2048;
        #2000000;
        $stop;
    end
endmodule