计算机组成原理VHDL语言实现16位ALU实验

计算机组成原理实验第二个，VHDL语言，ISE设计环境设计一个16位的ALU。
资源下载：
链接：https://pan.baidu.com/s/1cyhJ2ZynUMMFnYi2YOIMmA
提取码：0upp

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity alu is
    Port ( clk : in  STD_LOGIC;--时钟
           rst : in  STD_LOGIC;--复位
           In_A : in  STD_LOGIC_VECTOR (15 downto 0);--操作数A
			  In_B : in  STD_LOGIC_VECTOR (15 downto 0);--操作数B
           Out_Y : out  STD_LOGIC_VECTOR (15 downto 0);--输出
			  OP : in  STD_LOGIC_VECTOR(3 downto 0);--操作码
			  Flags :out STD_LOGIC_VECTOR(3 DOWNTO 0));--标志位为OF/CF/ZF/SF
end alu;

architecture Behavioral of alu is
    signal State:STD_LOGIC_VECTOR (1 downto 0):= "00";--记录当前的状态,来判断该进行什么操作
    signal int_A, int_B, int_Y : INTEGER RANGE 0 TO 65535:=0;
	 signal temp_A, temp_B, temp_Y : STD_LOGIC_VECTOR (15 downto 0);--定义临时操作数
	 
	 signal Flag_OF : STD_LOGIC;--溢出标志
    signal Flag_CF : STD_LOGIC;--进位标志
    signal Flag_ZF : STD_LOGIC;--0标志位
    signal Flag_SF : STD_LOGIC;--正负标志
	 signal M:  STD_LOGIC:='0';--扩展：对于带符号运算ADC/SBB
begin
    process(rst,clk)
	 begin
	     if (rst='1') then
		      State <= "00";
				Flag_OF <= '0';
            Flag_CF <= '0';
            Flag_ZF <= '0';
            Flag_SF <= '0';
				M <='0';
		  else
	     if (State = "00") then--状态1,读取A数字转换；
				temp_A <= In_A;
		      int_A <= CONV_INTEGER(In_A); --将A输入转化为整形
		      State <= "01";
		  end if;
		  if (State = "01") then--状态2,读取B数字转换；
		      int_B <= CONV_INTEGER(In_B);--将B输入转化为整形
				temp_B <= In_B;
				State <= "10";
		  end if;
        if (State = "10") then--状态3，进行运算；
		      CASE OP IS
                WHEN "0000" => --ADD加
                    Out_Y <= In_A + In_B;
						  temp_Y <= In_A + In_B;
						  M <= '1';
                    --int_Y := int_A + int_B;
                    --Out_Y <= CONV_STD_LOGIC_VECTOR(int_Y,16);
                    if(temp_A(15) = '0' and temp_B(15) = '0' and temp_Y(15) = '1') then --进行溢出和是否进位判断
						      Flag_OF <= '1'; 
						  end if;
                    if(temp_A(15)='1' and temp_B(15)='1' and temp_Y(15)='0') then --进行溢出和是否进位判断
						      Flag_OF <= '1'; 
						      Flag_CF <='1'; 
						  end if;
                    if(temp_Y = "0000000000000000") then --0标志位与0进行比较
						      Flag_ZF <= '1'; 
						  end if;
                    if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
						      Flag_SF <= '1'; 
						  end if;
                    State <= "11";
						  
                WHEN "0001" => --SUB减                 
                    int_Y <= int_A - int_B;                    
                    if(int_Y = 0) then 
						      Flag_ZF <= '1'; 
						  end if;
                    if(int_Y < 0) then 
						      Flag_SF <= '1'; 
						  end if;
                    Out_Y <= CONV_STD_LOGIC_VECTOR(int_Y,16); 
                    State <= "11";
						  
                WHEN "0010" => --AND逻辑与
                    Out_Y <= (In_A AND In_B);
						  temp_Y <= (In_A AND In_B);
                    if(CONV_INTEGER(temp_Y) = 0) then 
						      Flag_ZF <= '1';
							end if;
                    if(CONV_INTEGER(temp_Y) < 0) then 
						      Flag_SF <= '1'; 
						  end if;
                    State <= "11";
						  
                WHEN "0011" => --OR逻辑或
                    Out_Y <= In_A OR In_B;
                    State <= "11";
						  
                WHEN "0100" => --XOR逻辑异或
                    Out_Y <= In_A XOR In_B;
                    State <= "11";
						  
                WHEN "0101" => --NOT逻辑非
                    Out_Y <= NOT In_A;
                    State <= "11";
						  
                WHEN "0110" => --SLL逻辑左移
                    if(In_B = "0000") then
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SLL CONV_INTEGER(In_B(3 downto 0)));
                    else
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SLL 1);
                    end if;
                    State <= "11";
						  
                WHEN "0111" => --SLA算术左移
                   if(In_B = "0000") then
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SLA CONV_INTEGER(In_B(3 downto 0)));
                    else
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SLA 1);
                    end if;
                    State <= "11";
						  
                WHEN "1000" => --SRL逻辑右移
                    if(In_B = "0000") then
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SRL CONV_INTEGER(In_B));
                    else
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SRL 1);
                    end if;
                    State <= "11";
						  
                WHEN "1001" => --SRA算术右移
                    if(In_B(3 downto 0) = "0000") then
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SRA CONV_INTEGER(In_B(3 downto 0)));
                    else
                        Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) SRA 1);
                    end if;
                    State <= "11";
						  
                WHEN "1010" => --ROL循环逻辑左移
                      if(In_B(3 downto 0) = "0000") then
                          Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) ROL CONV_INTEGER(In_B(3 downto 0)));
                      else
                          Out_Y <= TO_STDLOGICVECTOR(To_bitvector(In_A) ROL 1);
                      end if;
							 State <= "11";
					 WHEN "1011" =>  --ADC带进位加法
					       if M ='1' then
					           Out_Y <= In_A + In_B + Flag_CF;
						        temp_Y <= In_A + In_B + Flag_CF;
								  M <='0';
							 end if;
					 WHEN "1100" =>  --SBB带进位减法
					       if M ='1' then
					           int_Y <= int_A - int_B;
						        Out_Y <= CONV_STD_LOGIC_VECTOR(int_Y,16) - Flag_CF;
								  M <='0';
							 end if;
					 WHEN OTHERS=>
					     Out_Y <= "1111111111111111";--默认报错用-1
                    State <= "11";					     
				end case; 	
		  end if;
        if State = "11" then--输出FLAGS;
		  Flags(3) <= Flag_OF;
		  Flags(2) <= Flag_CF;
		  Flags(1) <= Flag_ZF;
		  Flags(0) <= Flag_SF;
		  State <= "00";
		  end if;	
    end if;		  
	 end process;
end Behavioral;

仿真test文件：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test IS
END test;
 
ARCHITECTURE behavior OF test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT alu
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         In_A : IN  std_logic_vector(15 downto 0);
         In_B : IN  std_logic_vector(15 downto 0);
         Out_Y : OUT  std_logic_vector(15 downto 0);
         OP : IN  std_logic_vector(3 downto 0);
         Flags : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal In_A: std_logic_vector(15 downto 0) := (others => '0');
   signal In_B : std_logic_vector(15 downto 0) := (others => '0');
   signal OP : std_logic_vector(3 downto 0) := (others => '0');

 	--Outputs
   signal Out_Y : std_logic_vector(15 downto 0);
   signal Flags : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: alu PORT MAP (
          clk => clk,
          rst => rst,
          In_A => In_A,
          In_B => In_B,
          Out_Y => Out_Y