【计算机组成原理】使用Quartus完成十六位运算器ALU的设计

设计16位ALU运算器

要求

设计具有下列功能的16位ALU

功能选择输入func[3…0]	操作
0000	c←a and b
0001	c←a or b
0010	c←a xor b
0011	c←not a
0100	c←a+b
0101	c←a-b
其它	c←a

• 编写VHDL代码

编写VHDL代码

-- 十六位运算器的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity two_sixteenAU is
	port(a, b: in std_logic_vector(15 downto 0);
			func: in std_logic_vector(3 downto 0);
			c_linxuan: out std_logic_vector(15 downto 0));
end two_sixteenAU;

architecture behave of two_sixteenAU is
	begin
		process(a, b, func)
			begin 
				case func is
					when "0000" => c_linxuan <= a and b;
					when "0001" => c_linxuan <= a or b;
					when "0010" => c_linxuan <= a xor b;
					when "0011" => c_linxuan <= not a;
					when "0100" => c_linxuan <= a + b;
					when "0101" => c_linxuan <= a - b;
					when others => c_linxuan <= a;
				end case;
		end process;
end behave;