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`timescale 1ns / 1ps

module debouncing (
    input           	sys_clk,
    input       	sys_rst_n,
    input 		clk_flag,
    input		i_btn,
    output logic	o_btn
    );
       reg    delay0;
       reg    delay1;
	   reg    delay2;
       reg    delay3;
       reg    delay4;
		always_ff@(posedge sys_clk,