题目描述
See also: Serial receiver
Now that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is don’t-care otherwise.
Note that the serial protocol sends the least significant bit first.
代码
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
parameter idle=0,start=1,b1=2,b2=3,b3=4,b4=5,b5=6,b6=7,b7=8,b8=9,stop=10,error=11;
reg[3:0] state,next_state;
always@(*)
case(state)
idle:next_state=(~in)?start:idle;
start:next_state=b1;
b1:next_state=b2;
b2:next_state=b3;
b3:next_state=b4;
b4:next_state=b5;
b5:next_state=b6;
b6:next_state=b7;
b7:next_state=b8;
b8:next_state=in?stop:error;
stop:next_state=(~in)?start:idle;
error:next_state=in?idle:error;
endcase
always@(posedge clk)
if(reset)
state<=idle;
else
state<=next_state;
assign done = (state==stop);
// New: Datapath to latch input bits.
reg[7:0] temp;
always@(posedge clk)
if(reset)
temp <= 0;
else
case(state)
start:temp[0]<=in;
b1:temp[1]<=in;
b2:temp[2]<=in;
b3:temp[3]<=in;
b4:temp[4]<=in;
b5:temp[5]<=in;
b6:temp[6]<=in;
b7:temp[7]<=in;
endcase
assign out_byte = done?temp:0;
endmodule