Verilog 刷题-Fsm serialdata

 在上一题的基础上

case语句里添加一个将in值赋到out_byte[]即可。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
reg [5:0]state;
    reg [5:0]next_state;
    parameter w=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,stop=9,error = 10,str=11;
    always@(*)begin 
        case(state)
            w:next_state=in?w:str;
            str:begin next_state = s1;out_byte[0] = in;end
            s1:begin next_state = s2; out_byte[1] = in;end
            s2:begin next_state = s3; out_byte[2] = in;end
            s3:begin next_state = s4;out_byte[3] = in;end
            s4:begin next_state = s5;out_byte[4] = in;end
            s5:begin next_state = s6;out_byte[5] = in;end
            s6:begin next_state = s7;out_byte[6] = in;end
            s7:begin next_state = s8;out_byte[7] = in;end
            s8:next_state = in?stop:error;
            stop:next_state = in?w:str;
            error:next_state = in?w:error;
        endcase
    end
    always@(posedge clk)begin
        if(reset)state <= w;
        else state <= next_state;
    end
    assign done = (state == stop);
    // Use FSM from Fsm_serial

    // New: Datapath to latch input bits.

endmodule