Verilog刷题HDLBits——Exams/review2015 fsmshift

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本文链接：https://blog.csdn.net/weixin_45968042/article/details/128428752

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该博客介绍了如何使用Verilog设计一个有限状态机（FSM）和计数器来控制shift_register。在FSM中，当检测到特定序列时，shift_register被启用并保持4个时钟周期。提供了三种不同的实现方案，包括直接使用FSM和通过计数器来控制shift_ena信号。在重置状态下，shift_ena会持续4个周期，然后永久为0，除非再次重置。

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Verilog刷题HDLBits——Exams/review2015 fsmshift

题目描述
代码
结果

题目描述

This is the third component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.

Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).
在这里插入图片描述

代码

// 解法一 使用有限状态机
module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    
    parameter A=0,B=1,C=2,D=3,E=4;
    reg[2:0] state,next_state;
    
    always@(*)
        case(state)
            A:next_state=B;
            B:next_state=C;
            C:next_state=D;
            D:next_state=E;
            E:next_state=E;
        endcase
    
    always@(posedge clk)
        if(reset)
            state<=A;
    	else
            state<=next_state;
    
    assign shift_ena = ~(state==E);

endmodule

// 解法二 使用计数器
module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    
    reg[2:0] count;
    always@(posedge clk)
        if(reset)
            count<=0;
        else if(count>=4)
            count<=4;
        else
            count<=count+1;
    
    assign shift_ena = (count==0|count==1|count==2|count==3);

endmodule

// 解法三 根据计数器什么时候加什么时候不加
module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    
    reg [2:0] count;
    wire count_end;

    always@(posedge clk)
        if(reset)
            count<=0;
        else if(shift_ena)
            count<=count+1;
        else
            count<=0;

    assign count_end = shift_ena && (count==3);

    always@(posedge clk)
        if(reset)
            shift_ena<=1;
        else if(count_end)
            shift_ena<=0;

endmodule