Exams/review2015 fsmshift

https://hdlbits.01xz.net/wiki/Exams/review2015_fsmshift

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
	parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5;
    reg [2:0] cs,ns;
    
    always@(*)
        begin
            case(cs)
                S0:ns=reset?S1:S0;
                S1:ns=reset?S1:S2;
                S2:ns=reset?S1:S3;
                S3:ns=reset?S1:S4;
                S4:ns=reset?S1:S0;
            endcase
        end
    
    always @(posedge clk)
        begin
            cs<=ns;
        end
    assign shift_ena= ~(cs==S0);
endmodule