HDLbits--Exams/review2015 fsmshift

状态机控制器，当reset时输出四个周期；如果reset一直为1，则输出一直保持在第一个周期。 

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    
    parameter set0=0,b1=1,b2=2,b3=3,b4=4;
    reg [2:0] state,next_state;
    
    always@(*)
        begin
            case(state)
                b1:
                    next_state<=reset?b1:b2;
                b2:
                    next_state<=reset?b1:b3;
                b3:
                    next_state<=reset?b1:b4;
                b4:
                    next_state<=reset?b1:set0;
                set0:
                    next_state<=set0;
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                state<=b1;
            else
                state<=next_state;
        end
    
    assign shift_ena = state==b1||state==b2||state==b3||state==b4;

endmodule