# verilog设计一个分，秒定时器电路：输入时钟1KHZ进行分秒计数

## 代码部分

module clock
(
input wire         sys_clk     ,
input wire         sys_rst_n   ,

output reg [5:0]   cnt_s       ,
output reg [5:0]   cnt_m

);

reg [13:0]  cnt_1000;
reg    en_1;
reg    cnt_1m;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_1000 <= 12'd0;
else if(cnt_1000 == 999)
cnt_1000 <= 12'd0;
else
cnt_1000 <= cnt_1000 +12'd1;

always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
en_1 <= 1'b0;
else if (cnt_1000 == 998)
en_1 <= 1'b1;
else
en_1 <= 1'b0;

always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_s <= 6'd0;
else if (cnt_s == 6'd59)
cnt_s <= 6'd0;
else if(en_1 <= 1'b1)
cnt_s <= cnt_s +6'd1;
else
cnt_s <= cnt_s;

always@(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0)
cnt_1m <= 1'b0;
else if (cnt_s == 6'd59)
cnt_1m <= 1'b1;
else
cnt_1m <= 1'b0;
always@(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0)
cnt_m <= 6'd0;
else if(cnt_1m == 1'b1)
cnt_m <= 6'd1;
else
cnt_m <= 6'd0;

endmodule


## 模块例化演示代码

### 分频部分

module cnt_div
(
input wire         sys_clk     ,
input wire         sys_rst_n   ,

output reg         en_1

);
reg [13:0]  cnt_1000;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_1000 <= 12'd0;
else if(cnt_1000 == 999)
cnt_1000 <= 12'd0;
else
cnt_1000 <= cnt_1000 +12'd1;

always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
en_1 <= 1'b0;
else if (cnt_1000 == 998)
en_1 <= 1'b1;
else
en_1 <= 1'b0;

endmodule


### 60进制计数器部分

module cnt_60
(
input wire         sys_clk     ,
input wire         sys_rst_n   ,
input  wire         en_1       ,
output reg [5:0]   cnt_s       ,
output reg         cnt_1m

);

always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_s <= 6'd0;
else if (cnt_s == 6'd59)
cnt_s <= 6'd0;
else if(en_1 <= 1'b1)
cnt_s <= cnt_s +6'd1;
else
cnt_s <= cnt_s;

always@(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0)
cnt_1m <= 1'b0;
else if (cnt_s == 6'd59)
cnt_1m <= 1'b1;
else
cnt_1m <= 1'b0;

endmodule


### 顶端调用例化模块

module clock_static
(
input wire         sys_clk     ,
input wire         sys_rst_n   ,

output wire [5:0]   cnt_s       ,
output wire [5:0]   cnt_m

);

cnt_div
(
.sys_clk   (sys_clk) ,
.sys_rst_n (sys_rst_n) ,

.en_1      (en_1)

);

cnt_60  second
(
. sys_clk  (sys_clk) ,
. sys_rst_n(sys_rst_n) ,
.  en_1    (en_1) ,
. cnt_s    (cnt_s) ,
. cnt_1m   (cnt_1m)

);
cnt_60  minutes
(
. sys_clk    (sys_clk),
. sys_rst_n  (sys_rst_n),
.  en_1      (cnt_1m),
. cnt_s      (cnt_m),
. cnt_1m     ()

);

endmodule


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