名称:定时器的设计Verilog代码Quartus仿真(文末获取)
软件:Quartus
语言:Verilog
代码功能:
1. 工程文件
2. 程序文件
3. 程序编译
4. RTL图
5. Testbench
6. 仿真图
整体仿真图
分频模块
设置当前模式模块
计时模块
响铃模块
部分代码展示:
`timescale 1 ns/ 1 ns module timmer_tb(); reg CLK; reg HRS; reg MINS; reg RST; reg SET_ALARM; reg SET_TIME; reg TOGGLE_SWITCH; // wires wire SPEAKER_OUT; wire [7:0] hour_alarm; wire [7:0] hour_time; wire [7:0] minute_alarm; wire [7:0] minute_time; wire [7:0] second_alarm; wire [7:0] second_time; // assign statements (if any) timmer i1 ( // port map - connection between master ports and signals/registers .CLK(CLK), .HRS(HRS), .MINS(MINS), .RST(RST), .SET_ALARM(SET_ALARM), .SET_TIME(SET_TIME), .SPEAKER_OUT(SPEAKER_OUT), .TOGGLE_SWITCH(TOGGLE_SWITCH), .hour_alarm(hour_alarm), .hour_time(hour_time), .minute_alarm(minute_alarm), .minute_time(minute_time), .second_alarm(second_alarm), .second_time(second_time) ); //input SET_TIME,//设置时间,高有效 //input SET_ALARM,//设置闹铃时间,高有效 //input HRS,//设置小时,高有效 //input MINS,//设置分钟,高有效 //input TOGGLE_SWITCH,//打开、关闭报时控制,高有效 initial begin RST=0; HRS=0;// MINS=0;// SET_ALARM=0;// SET_TIME=0;// TOGGLE_SWITCH=1;// #100; RST=1; #100; SET_TIME=1;//设置时间,高有效 #10; SET_TIME=0; #40; HRS=1;//设置小时,高有效 #10; HRS=0; #40; HRS=1;//设置小时,高有效 #10; HRS=0; #40; MINS=1;//设置分钟,高有效 #10; MINS=0; #40; MINS=1;//设置分钟,高有效 #10; MINS=0; #40; MINS=1;//设置分钟,高有效 #10; MINS=0; #40; SET_TIME=1;//设置时间完成 #10; SET_TIME=0; #40; #1000; SET_ALARM=1;//设置闹铃时间,高有效 #10; SET_ALARM=0; #40; HRS=1;//设置小时,高有效 #10; HRS=0; #40;
源代码
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