HDLbits--Cs450/timer

 计数器 当load为1时加载数据 为0倒计时

module top_module(
	input clk, 
	input load, 
	input [9:0] data, 
	output tc
);
    reg [9:0] counter;
    always@(posedge clk)
        begin
            if(load)
                counter<=data;
            else
                begin
            		if(counter>0)
                		counter<=counter-1;
        		end
        end
    assign  tc= counter==0?1:0;

endmodule