在formality flow 中的match step 前有一步preverify :
Preverify mode can be used to perform setup operations on post-SVF modified design objects.
However only setup operations that do not modify the design database can be perform.
Such as preverify mode alleviates this problem by giving you access to the post-SVF processed register name.
预验证模式可用于对SVF修改后的design执行设置操作。但是,只能setup operations,不能修改design database。preverify模式通过允许您访问经过SVF处理后的寄存器名称来缓解这个问题