6-2—时序逻辑的测试模块

一、实验目的：用Quartus软件与Modlsim进行对一个四位的并串转换模块进行测试。

二、实验原理代码图:
1：设计模块代码
2:测试模块代码

三、实验工具：Quartus软件、Modlsim软件、pc机。
四、实验截图：
五、实验视频
https://www.bilibili.com/video/BV1u64y1R7KV?share_source=copy_web

六、实验代码
1.设计模块代码
module p2s (data_ in, clock, reset, load, data out, done);
input [3:0] data_ in;
input clock, reset, load;
output data out;
output done;reg done;
reg [3:0] temp;reg [3:0] cnt;
always@ (posedge clock or posedge reset,begin
if (reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if (load)
begin
temp<=data_ in;
cnt<=0;
done<=0;
end
else if (ent3)
begin
temp <= {temp[2:0],1’b0};
cnt<=0;
done<=1;
end
else
begin
temp <= {temp[2:0],1’b0};
cnt<=cnt+1;
done<=0;
end
end
assign data_ out= (done1)?1 'bz:temp[3];
endmodule
2.测试模块代码
module tbp2s;
reg [3:0] data_ in;
reg clock, reset, load;
wire data_ out;
wire done;
initial
begin
reset=1;
#15 reset=0;end
initial clock=1;
always #5 clock=~clock;
always @ (done)
begin
if (done1)
begin
data_ in=Srandom16;
load=1;
end
else
begin
load=0;
end
end
always @ (posedge clock)
if (load1)
begin:dis
integer i;
i=3;
repeat (4)
begin
@ (posedge clock)
if (data_ out==data_ in[i])
$display (“Output Right!”) ;
else
$display (“Bad Output!data out= 号b ,but data in[8&d]= 8b”,data in[i]);
i=i-1;
end
end
p2s ip2s (data_ in, clock, reset, load,data out, done);endmodule
七、软件下载网站：

1、Quartus软件下载链接：
https://pan.baidu.com/s/1k_pr6xnKMZyzAh_nyej7yQ 提取码:7330
2、Modelsim 10.x软件下载链接：
https://pan.baidu.com/s/1PoKk4W_SG7Zqp9KNuwLdTQ
提取码：m7ja