数字电路ppt复习

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNTMOD12 IS
PORT(
	CLK,EN,CLR:IN STD_LOGIC;
	QA,QB,QC,QD:OUT STD_LOGIC
);
END CNTMOD12;

ARCHITECTURE RTL OF CNTMOD12 IS
SIGNAL CNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
QD<=CNT(3);
QC<=CNT(2);
QB<=CNT(1);
QA<=CNT(0);
PROCESS(CLK,CLR)
BEGIN
	IF CLR='1' THEN CNT<="0000";
	ELSIF CLK'EVENT AND CLK='1' THEN
		IF EN='0' THEN CNT<=CNT;
		ELSE
			IF CNT="1011" THEN CNT<="0000";
			ELSE CNT<=CNT+'1';
			END IF;
		END IF;
	END IF;
END PROCESS;
END RTL;

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