数字电路ppt复习二

 

LIBRARY IEEE;
USE STD_LOGIC_1164.ALL;
USE STD_LOGIC_UNSIGNED.ALL;

ENTITY DIV12 IS
PORT(
	CLK:IN STD_LOGIC;
	DIV1,DIV2,DIV3:OUT STD_LOGIC
);
END DIV12;

ARCHITECTURE RTL OF DIV12 IS
SIGNAL CNT:INTEGER RANGE 0 TO 15;
BEGIN
PROCESS(CLK)
BEGIN
	IF CLK'EVENT AND CLK='1' THEN 
		IF CNT=11 THEN CNT<=0;
		ELSE CNT<=CNT+1;
		END IF;
	END IF;
END PROCESS;

PROCESS(CNT)
BEGIN
	CASE CNT IS
	WHEN 0 TO 5=>DIV1<='1';
	WHEN 6 TO 11=>DIV1<='0';
	WHEN OTHERS=>DIV1<='0';
	END CASE;
END PROCESS;

PROCESS(CNT)
BEGIN
	CASE CNT IS
	WHEN 1 TO 6=>DIV2<='1';
	WHEN 7 TO 11|0=>DIV2<&#