基于System-Verilog的FPGA设计与仿真

流水灯

Verilog代码

module led_chaser(
    input wire clk,
    input wire rst,
    output reg [7:0] leds
);

always @(posedge clk or posedge rst) begin
    if (rst) begin
        leds <= 8'b00000001;
    end else begin
        leds <= {leds[6:0], leds[7]};
    end
end

endmodule

System Verilog改写

module led_chaser(
    input logic clk,
    input logic rst,
    output logic [7:0] leds
);

always_ff @(posedge clk or posedge rst) begin
    if (rst) begin
        leds <= 8'b00000001;
    end else begin
        leds <= {leds[6:0], leds[7]};
    end
end

endmodule

Testbench

module tb_led_chaser;
    logic clk;
    logic rst;
    logic [7:0] leds;

    led_chaser uut (
        .clk(clk),
        .rst(rst),
        .leds(leds)
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        rst = 1;
        #10;
        rst = 0;
        #100;
        $stop;
    end
endmodule

全加器

Verilog代码

module full_adder (
    input wire a,
    input wire b,
    input wire cin,
    output wire sum,
    output wire cout
);

assign {cout, sum} = a + b + cin;

endmodule

System Verilog改写

module full_adder (
    input logic a,
    input logic b,
    input logic cin,
    output logic sum,
    output logic cout
);

assign {cout, sum} = a + b + cin;

endmodule

Testbench

module tb_full_adder;
    logic a, b, cin;
    logic sum, cout;

    full_adder uut (
        .a(a),
        .b(b),
        .cin(cin),
        .sum(sum),
        .cout(cout)
    );

    initial begin
        a = 0; b = 0; cin = 0;
        #10; a = 0; b = 1; cin = 0;
        #10; a = 1; b = 0; cin = 0;
        #10; a = 1; b = 1; cin = 0;
        #10; a = 0; b = 0; cin = 1;
        #10; a = 0; b = 1; cin = 1;
        #10; a = 1; b = 0; cin = 1;
        #10; a = 1; b = 1; cin = 1;
        #10; $stop;
    end
endmodule

超声波测距

Verilog代码

module ultrasonic_distance (
    input wire clk,
    input wire rst,
    input wire echo,
    output wire trig,
    output wire [15:0] distance
);

// Implementation of ultrasonic distance measurement here

endmodule

System Verilog改写

module ultrasonic_distance (
    input logic clk,
    input logic rst,
    input logic echo,
    output logic trig,
    output logic [15:0] distance
);

// Implementation of ultrasonic distance measurement here

endmodule

Testbench

module tb_ultrasonic_distance;
    logic clk;
    logic rst;
    logic echo;
    logic trig;
    logic [15:0] distance;

    ultrasonic_distance uut (
        .clk(clk),
        .rst(rst),
        .echo(echo),
        .trig(trig),
        .distance(distance)
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        rst = 1;
        #10;
        rst = 0;
        #2000;
        $stop;
    end
endmodule