HDLBits--model

module

直接实例化即可

module top_module ( input a, input b, output out );
    mod_a instance1(.out(out),.in1(a),.in2(b));
endmodule

Module_pos

按照位置来实例化

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a instance1(out1,out2,a,b,c,d);
endmodule

Module_name

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a instance1(
        .in1(a),
        .in2(b),
        .in3(c),
        .in4(d),
        .out1(out1),
        .out2(out2)
    );
endmodule

Module_shift

module top_module ( input clk, input d, output q );
    wire q1,q2;
    my_dff dff1(clk,d,q1);
    my_dff dff2(clk,q1,q2);
    my_dff dff3(clk,q2,q);
endmodule

Module_shift8

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
	wire [7:0] q1,q2,q3;
    my_dff8 dff1(clk,d,q1);
    my_dff8 dff2(clk,q1,q2);
    my_dff8 dff3(clk,q2,q3);
    always @(*)begin
        case(sel)
            2'b00: q<=d;
            2'b01: q<=q1;
            2'b10: q<=q2;
            2'b11: q<=q3;
        endcase
    end
endmodule

Module_add

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
	wire cout1;
    add16 add1(
        .a(a[15:0]),
        .b(b[15:0]),
        .cin(1'b0),
        .cout(cout1),
        .sum(sum[15:0]));
    add16 add2(
        .a(a[31:16]),
        .b(b[31:16]),
        .cin(cout1),
        .cout(),
        .sum(sum[31:16]));
endmodule

Module_fadd

注意这里是不需要你编写add16模块内部的
相当于默认已经把add16内部的16个add1连接完成
只需要你设计add1内部

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout1;
    add16 add_16(
                .a(a[15:0]),
                .b(b[15:0]),
                .cin(0),
                .sum(sum[15:0]),
                .cout(cout1)
    );
    add16 add_32(
                .a(a[31:16]),
                .b(b[31:16]),
       			 .cin(cout1),
                .sum(sum[31:16]),
                .cout()
    );

endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );
    assign {cout,sum} = a+b+cin;
    //或采用逻辑表达式
    //assign sum = a^b^cin;
    //assign cout = cout = a&b | a&cin | b&cin；
endmodule

Module_cseladd

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire sel;
    wire [31:16] sum1,sum2;
    add16 add16_0(
                .a(a[15:0]),					
                .b(b[15:0]),
        		.cin(1'b0),
                .sum(sum[15:0]),
                .cout(sel)
);
     add16 add16_1(
                 .a(a[31:16]),					
                 .b(b[31:16]),
         		.cin(1'b0),
         		.sum(sum1[31:16]),
                .cout()
);
    add16 add16_2(
                .a(a[31:16]),					
                .b(b[31:16]),
        		.cin(1'b1),
                .sum(sum2[31:16]),
                .cout()
);
    
    always @(sel)begin
        case(sel)
        	1'b0: sum[31:16] = sum1[31:16];
        	1'b1: sum[31:16] = sum2[31:16];
			default :sum <= 1'b0;            
        endcase
    end
    //assign sum[31:16] = sel?sum2:sum1;//也可以使用case语句
endmodule

Module_addsub

有复制操作

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire cout1;
    wire[31:0] bb;
    assign bb = b^{32{sub}};
    add16 add1(
        .a(a[15:0]),
        .b(bb[15:0]),
        .cin(sub),
        .sum(sum[15:0]),
        .cout(cout1)
    );
	add16 add2(
        .a(a[31:16]),
        .b(bb[31:16]),
        .cin(cout1),
        .sum(sum[31:16]),
        .cout()
    );
endmodule