`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/09/16 08:31:14
// Design Name:
// Module Name: tube1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module tube1(
input [3:0] switch,
output reg [6:0] led,
output reg [3:0] p
);
always@(switch[0])
begin
p[0] = switch[0];
case(switch[0])
1'b0:
begin
led = 7'b1001111;
end
1'b1:
begin
led = 7'b1111111;
end
endcase
end
always@(switch[1])
begin
p[1] = switch[1];
case(switch[1])
1'b0:
begin
led = 7'b0010010;
end
1'b1:
begin
led = 7'b1111111;
end
endcase
end
always@(switch[2])
begin
p[2] = switch[2];
case(switch[2])
1'b0:
begin
led = 7'b0000110;
end
1'b1:
begin
led = 7'b1111111;
end
endcase
end
always@(switch[3])
begin
p[3] = switch[3];
case(switch[3])
1'b0:
begin
led = 7'b1001100;
end
1'b1:
begin
led = 7'b1111111;
end
endcase
end
endmodule
报错如下:
[Synth 8-4485] pin switch[3] is connected to multiply driven net where other driver is constant
大概的意思是switch[3]这个引脚连了多个驱动器,并且还有常量驱动,猜测因为没有初始化,但代码本身有很多问题。下面是正确的代码:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/09/16 08:31:14
// Design Name:
// Module Name: tube1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module tube1(
input clk,
input [3:0] switch,
output reg [6:0] led,
output reg [3:0] p
);
reg [29:0] count;
always@(posedge clk)
begin
if (!switch)
begin
p=4'b1111;
count<=0;
end
else if (count==100000)
begin
if (switch[0])
begin
p=4'b1111;
p[0] = ~switch[0];
led = 7'b1001111;
end
count <= count + 1;
end
else if (count==200000)
begin
if (switch[1])
begin
p=4'b1111;
p[1] = ~switch[1];
led = 7'b0010010;
end
count <= count + 1;
end
else if (count==300000)
begin
if(switch[2])
begin
p=4'b1111;
p[2] = ~switch[2];
led = 7'b0000110;
end
count <= count + 1;
end
else if (count==400000)
begin
if (switch[3])
begin
p=4'b1111;
p[3] = ~switch[3];
led = 7'b1001100;
end
count <= 0;
end
else
begin
count <= count+1;
end
end
endmodule
最好考虑把count计数器单独拿出去,不容易出错。
代码如下:
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/09/16 08:31:14
// Design Name:
// Module Name: tube1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module tube1(
input clk,
input [3:0] switch,
output reg [6:0] led,
output reg [3:0] p
);
reg [29:0] count;
always@(posedge clk)
begin
count <= count + 1;
if (count==400001)
begin
count <=0;
end
end
always@(posedge clk)
begin
if (!switch)
begin
p=4'b1111;
end
else if (count==100000)
begin
if (switch[0])
begin
p=4'b1111;
p[0] = ~switch[0];
led = 7'b1001111;
end
end
else if (count==200000)
begin
if (switch[1])
begin
p=4'b1111;
p[1] = ~switch[1];
led = 7'b0010010;
end
end
else if (count==300000)
begin
if(switch[2])
begin
p=4'b1111;
p[2] = ~switch[2];
led = 7'b0000110;
end
end
else if (count==400000)
begin
if (switch[3])
begin
p=4'b1111;
p[3] = ~switch[3];
led = 7'b1001100;
end
end
end
endmodule