verilog实现乒乓RAM的两种方式

方式1：单符号数据交替写入和输出。单符号指每次只存储和读出一位多bit位宽的数据，比如每次只读取一个[7:0]data；

`timescale 1 ns / 1 ps

module pingpang (
	input            clk,
	input            rst_n,	 
	input            wr_val,
	input      [10:0] data_in,   // 输入数据
	output reg [10:0] data_out   // 输出数据		
	);	  	
	parameter ram_depth = 4;		 
	
	reg [2:0] cur_st,next_st;	
	
	parameter idle = 3'b000;
	parameter w_ram1_st = 3'b001;
	parameter r_ram1_st = 3'b010; 
	
	wire w_ram1,r_ram1,w_ram2,r_ram2;
	reg [10:0] data_in_dly;	
	reg wr_val_dly,wr_val_dly2;				 
	reg [10:0] ram1,ram2;
	
	
	always @(posedge clk,negedge rst_n)
		begin
			if(!rst_n) 
				begin
					cur_st <= idle;	
					data_in_dly <= 0;  
					wr_val_dly <= 0;
					wr_val_dly2 <= 0;
				end
			else
				begin
					cur_st <= next_st;
					data_in_dly <= data_in;
					wr_val_dly  <= wr_val;
					wr_val_dly2 <= wr_val_dly;
				end
		end
	
	always @(*)
		begin
			case(cur_st)								  
				idle      : next_st <= wr_val?w_ram1_st:idle; 	//每次只存一个数据，然后立马开始读
				w_ram1_st : next_st <= r_ram1_st;
				r_ram1_st : next_st <= wr_val?w_ram1_st:idle;		
				default   : next_st <= idle;					  
			endcase
		end	
	
	assign w_ram1 = cur_st == w_ram1_st?1:0; 
	assign r_ram1 = cur_st == r_ram1_st?1:0;
	assign w_ram2 = ~w_ram1 && wr_val_dly;