话说玩这块板子,也有好长时间了,实在是不怎么溜。连数据显示都搞了很久,这可是数据的一扇窗户啊。
不能看始终不过瘾是不。
好像大多使用的还是VGA的驱动方式,更通用,更简单。但是现在可是高清的时代,好歹也要跟上高清的步伐啊。
虽然官方提供了 好几个 HDMI的历程,不过,我看到那么多ip和,编译一次,好几十分钟,也是。。。
先写HDMI的时序,我这里用的是1280*720的的分辨率,其他的需要自己修改一下,包括像素时钟
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Create Date: 06:01:06 10/02/2013
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zedboard_hdmi is
Port ( clk_100 : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
colour : in STD_LOGIC_VECTOR (23 downto 0);
hdmi_d : out STD_LOGIC_VECTOR (15 downto 0);
hdmi_de : out STD_LOGIC;
hdmi_int : in STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC);
end zedboard_hdmi;
architecture Behavioral of zedboard_hdmi is
COMPONENT i2c_sender
PORT(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
END COMPONENT;
signal blanking : std_logic := '0';
signal hsync : std_logic := '0';
signal vsync : std_logic := '0';
signal edge : std_logic := '0';
-- signal colour : STD_LOGIC_VECTOR (23 downto 0);
signal Y : STD_LOGIC_VECTOR (15 downto 0);
signal Cr : STD_LOGIC_VECTOR (15 downto 0);
signal Cb : STD_LOGIC_VECTOR (15 downto 0);
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal hcounter : unsigned(10 downto 0) := (others => '0');
signal vcounter : unsigned(10 downto 0) := (others => '0');
constant ZERO : unsigned(10 downto 0) := (others => '0');
signal hVisible : unsigned(10 downto 0);
signal hS