ZedBoard教程PL篇(4):hdmi芯片AD7511输出显示彩条

开发板环境：vivado2017.4

开发板：Zedboard 芯片型号：xc7z020clg484-1

本章主要使用HDMI芯片AD7511输出显示彩条

可以从上面这个图可以看出整个工程大致工作原理，以v-tc核产生hdmi驱动的时序，v-tc产生的是RGB时序和hdmi输入的波形有出入，所以需要将hsync和vsync处理一下

其中hdmi核为官方提供的ip，hdmi核也提供了ad7511的iic接口配置，按不同的按键可以切换不同的颜色

V-TC模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/26 13:57:00
// Design Name: 
// Module Name: v_tc_data
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module v_tc_data(
input           clk,
input           resetn,
input           key,
output          hsync,
output          vsync,
output  [23:0]  data_out,
output          de
    );
    


wire      hsync_out;
wire      vsync_out;
wire      active_video_out;  
v_tc_0 your_instance_name (
      .clk(clk),                            // input wire clk
      .clken(1'b1),                        // input wire clken
      .gen_clken(1'b1),                // input wire gen_clken
      .hsync_out(hsync_out),                // output wire hsync_out
      .hblank_out(),              // output wire hblank_out
      .vsync_out(vsync_out),                // output wire vsync_out
      .vblank_out(),              // output wire vblank_out
      .active_video_out(active_video_out),  // output wire active_video_out
      .resetn(resetn),                      // input wire resetn
      .fsync_out()                // output wire [0 : 0] fsync_out
    );    

wire     key_out_flag;   
key_test key_test_inst(
    .clock(clk),//100M
    .reset(resetn),//SW0
    .key_in(key),//BTNC
    .key_out_flag(key_out_flag)
        );    

reg [15:0]  data_out_reg;
reg [1:0]   sel; 
reg [23:0]  data_color; 
reg [23:0]	 color_bar;  
always@(posedge clk or negedge resetn)begin
        if(!resetn)    
            sel    <=  2'd0;
        else if(key_out_flag)
            sel    <=  sel + 1'd1;
        else
            sel    <=  sel;
end

always@(posedge clk or negedge resetn)begin
        if(!resetn)    
            data_out_reg    <=  16'd0;
        else if(active_video_out)
            data_out_reg    <=  data_out_reg + 16'd1;
        else
            data_out_reg    <=  16'd0;
end 

always@(posedge clk or negedge resetn)begin
        if(!resetn)    
            data_color    <=  24'd0;
        else if(sel == 0)
            data_color    <=  24'h0000ff;
        else if(sel == 1)
            data_color    <=  24'h00ff00;
        else if(sel == 2)
            data_color    <=  24'hff0000; 
        else if(sel == 3)
            data_color    <=  color_bar;                           
        else
            data_color    <=  data_color;
end

always @(posedge clk or negedge resetn)begin
        if(!resetn)    
            color_bar    <=  24'h0;
        else if(data_out_reg==0)
            color_bar	<=	24'h0000ff;
        else if(data_out_reg==160)
            color_bar	<=	24'h00ff00;
        else if(data_out_reg==320)
            color_bar	<=	24'h00ffff;
        else if(data_out_reg==480)
            color_bar	<=	24'hff0000;
        else if(data_out_reg==640)
            color_bar	<=	24'hff00ff;
        else if(data_out_reg==800)
            color_bar	<=	24'hffff00;
        else if(data_out_reg==960)
            color_bar	<=	24'hffffff;
        else if(data_out_reg==1120)
            color_bar    <=  24'h000000;	   
        else
            color_bar	<=	color_bar;
end              

assign  hsync = !hsync_out;   
assign  vsync = !vsync_out;
assign  de = active_video_out;
assign  data_out = (active_video_out)? data_color:24'd0;

    
endmodule

按键检测模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/02/26 12:48:48
// Design Name: 
// Module Name: key_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//
 
 
module key_test(
input           clock,//100M
input           reset,//SW0
input           key_in,//BTNC
output          key_out_flag
    );
   
     
    
    reg         key_in_r1;
    reg         key_in_r2;
    wire        key_in_flag;
    
    reg         key_out;
    reg         key_out_r1; 
    reg         key_out_r2;
    
    reg [19:0]  cnt;
    reg [7:0]   led_reg;   

     
    
    always @ (posedge clock, negedge reset)
            if(!reset) 
                key_in_r1 <= 1'b1;
            else        
                key_in_r1 <= key_in;
     
    
    always @ (posedge clock, negedge reset)
            if(!reset) 
                key_in_r2 <= 1'b1;
            else        
                key_in_r2 <= key_in_r1;
    
    assign key_in_flag = (!key_in_r2 & key_in_r1); 
    
    always @ (posedge clock, negedge reset)
            if(!reset)
                cnt <= 20'h0;
            else if(key_in_flag)
                cnt <= 20'h0;
            else
                cnt <= cnt + 1'b1;
    
    always @ (posedge clock, negedge reset)
            if(!reset)
                key_out <= 1'b1;
            else if(cnt == 20'hfffff)            
                key_out <= key_in;
     
    
    always @ (posedge clock, negedge reset)
            if(!reset)
                key_out_r1 <= 1'b1;
            else
                key_out_r1 <= key_out;
    
    always @ (posedge clock, negedge reset)
            if(!reset)
                key_out_r2 <= 1'b1;
            else
                key_out_r2 <= key_out_r1;
    
assign  key_out_flag =  key_out_r1 && !key_out_r2;  
 

               
endmodule

顶层模块

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/06 11:39:21
// Design Name: 
// Module Name: hdmi_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module hdmi_top(
input           clock,//100M
input           key,//BTNC
input           reset,//BTNL
output          hdmi_hs,
output          hdmi_vs,
output          hdmi_de,
output  [15:0]  hdmi_data,
output          hdmi_clk,
output          hdmi_scl,
inout           hdmi_sda,
output          led


);

 
wire            vga_clk;//74.25M
wire            vga_clk_90;//74.25M
wire            i2c_clk;//100M
wire            locked;
        
assign led = !reset;

  clk_wiz_0 clk_wiz_0_inst
       (
        // Clock out ports
        .clk_out1(vga_clk),     // output clk_out1
        .clk_out2(vga_clk_90),     // output clk_out2
        .clk_out3(i2c_clk),     // output clk_out3
        // Status and control signals
        .reset(reset), // input resetn
        .locked(locked),       // output locked
       // Clock in ports
        .clk_in1(clock));      // input clk_in1            
    
  
wire            hsync;
wire            vsync;
wire            de;     
wire    [23:0]  data_out;
v_tc_data v_tc_data_inst(
        .clk(vga_clk),
        .resetn(locked),
        .key(key),
        .hsync(hsync),
        .vsync(vsync),
        .data_out(data_out),
        .de(de)
    );


hdmi_display_0  u_hdmi_display
(
    .i2c_clk            (i2c_clk),
    .vga_clk            (vga_clk),
    .vga_clk_90         (vga_clk_90),
    .rgb_in             (data_out),
    .hsync_in           (hsync),
    .vsync_in           (vsync),
    .de_in              (de),
    .hdmi_clk           (hdmi_clk),
    .hdmi_hsync         (hdmi_hs),
    .hdmi_vsync         (hdmi_vs),
    .hdmi_d             (hdmi_data),
    .hdmi_de            (hdmi_de),
    .hdmi_scl           (hdmi_scl),
    .hdmi_sda           (hdmi_sda)
);


      
endmodule

时序约束

set_property PACKAGE_PIN Y9 [get_ports clock]
set_property PACKAGE_PIN N15 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports clock]
set_property IOSTANDARD LVCMOS33 [get_ports reset]

set_property IOSTANDARD LVCMOS33 [get_ports key]
set_property PACKAGE_PIN P16 [get_ports key]

set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property PACKAGE_PIN T22 [get_ports led]

###############################################################
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports hdmi_clk]
set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_vs]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_hs]
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_de]
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[0]}]
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[1]}]
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[2]}]
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[3]}]
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[4]}]
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[5]}]
set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[6]}]
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[7]}]
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[8]}]
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[9]}]
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[10]}]
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[11]}]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[12]}]
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[13]}]
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[14]}]
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports {hdmi_data[15]}]

set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_scl]
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_sda]
set_property PULLUP true [get_ports hdmi_sda]

硬件hdmi芯片

hdmi输出接口

每次按KEY按键会切换不同的颜色

 下载bit文件（注意最好下载程序前先将开发板HDMI接口和电脑插好，否则有可能下载后不能正常显示）

开发板上电运行

上电后默认显示的第一幅图像

 按一下KEY后，显示第二幅图像

按一下KEY后，显示第三幅图像 

 按一下KEY后，显示第四幅图像