FPGA学习笔记 -- 层次化设计

自下而上：由功能单元到模块到整体

自上而下：由整体分解到功能模块

实际中两种思想是混合使用的：

        

案例：

全加器：

        

利用半加器实现

 

半加器模块

module half_add
(
	input wire in_1,
	input wire in_2,
	
	output wire sum,
	output wire count
);
	
	assign {count, sum} = in_1 + in_2;

endmodule

 全加器引用半加器

module full_adder
(
	input wire in0,
	input wire in1,
	input wire cin,
	
	output wire count,
	output wire sum
);

wire sum_0;
wire count_0;
wire count_1;

half_add half_0
(
	.in_1(in0),
	.in_2(in1),
	
	.sum(sum_0),
	.count(count_0)
);

half_add half_1
(
	.in_1(sum_0),
	.in_2(cin),
	
	.sum(sum),
	.count(count_1)
);

assign count = (count_0 | count_1);

endmodule

注意需要在file选项中选择全加器作为顶层设计

测试wen'j

`timescale 1ns/1ns

module tb_full_adder;

	reg in_1;
	reg in_2;
	reg cin;
	
	wire sum;
	wire count;
	
	initial
		begin
			in_1 <= 1'b0;
			in_2 <= 1'b0;
			cin <= 1'b0;
		end
	initial
		begin
			$timeformat(-9,0,"ns",6);
			$monitor("@time %t:in_1=%b,in_2=%b,cin=%b,sum=%b,count=%b",$time,in_1,in_2,cin,sum,count);
		end
	always #10 in_1 <= {$random} % 2;
	always #10 in_2 <= {$random} % 2;
	always #10 cin <= {$random} % 2;
	
	full_adder full_adder_0
	(
		.in0(in_1),
		.in1(in_2),
		.cin(cin),
		
		.count(count),
		.sum(sum)
		
	);

endmodule