mips简介

MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems).

 There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). As of April 2017, the current version is MIPS32/64 Release 6.[3][4]

MIPS is a load/store architecture (also known as a register-register architecture); except for the load/store instructions used to access memory, all instructions operate on the registers.

MIPS I[edit]

The first version of the MIPS architecture was designed by MIPS Computer Systems for its R2000 microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985.[citation needed] When MIPS II was introduced, MIPS was renamed MIPS I to distinguish it from the new version.[2]:32

MIPS II[edit]

MIPS II removed the load delay slot[2]:41 and added several sets of instructions. For shared-memory multiprocessing, the Synchronize Shared MemoryLoad Linked Word, and Store Conditional Word instructions were added. A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given branch-likely versions that executed the instruction in the branch delay slot only if the branch is taken.[2]:40 These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot.[2]:212 Doubleword load and store instructions for COP1–3 were added. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned.

The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the Floating Point Control and Status Register.

MIPS Computer SystemsR6000 microprocessor (1989) is the first MIPS II implementation.[2]:8

MIPS III[edit]

MIPS III is a backwards-compatible extension of MIPS II that added support for 64-bit memory addressing and integer operations. The 64-bit data type is called a doubleword, and MIPS III extended the general-purpose registers, HI/LO registers, and program counter to 64 bits to support it. New instructions were added to load and store doublewords, to perform integer addition, subtraction, multiplication, division, and shift operations on them, and to move doubleword between the GPRs and HI/LO registers. Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. Among those instructions redefined was Load Word. In MIPS III it sign-extends words to 64 bits. To complement Load Word, a version that zero-extends was added.

MIPS Computer SystemsR4000 microprocessor (1991) was the first MIPS III implementation.

MIPS IV[edit]

MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS. MIPS IV was designed to mainly improve floating-point (FP) performance. To improve access to operands, an indexed addressing mode (base + index, both sourced from GPRs) for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes).

The first MIPS IV implementation was the MIPS Technologies R8000 microprocessor chipset (1994). 

MIPS V[edit]

Announced on 21 October 1996 at the Microprocessor Forum 1996 alongside the MIPS Digital Media Extensions (MDMX) extension, MIPS V was designed to improve the performance of 3D graphics transformations.[10] In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from SGI. MIPS V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications.[11]

MIPS V implementations were never introduced. 

MIPS32/MIPS64

When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Up to MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem,[citation needed] and the architecture definition was changed to define a 32- and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999.[13]MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V.[13]

MIPS32/MIPS64 Release 1[edit]

The first release of MIPS32, based on MIPS II, added conditional moves, prefetch instructions, and other features from the R4000 and R5000 families of 64-bit processors.[13] The first release of MIPS64 adds a MIPS32 mode to run 32-bit code.[13] The MUL and MADD (multiply-add) instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were cache control instructions.[13]

MIPS32/MIPS64 Release 2[edit]

MIPS32/MIPS64 Release 3[edit]

MIPS32/MIPS64 Release 5[edit]

Announced on December 6, 2012.[14] Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures.[15]

MIPS32/MIPS64 Release 6[edit]

MIPS32/MIPS64 Release 6 in 2014


参考资料:

wiki:https://en.wikipedia.org/wiki/MIPS_architecture

          https://en.wikipedia.org/wiki/List_of_MIPS_architecture_processors

          https://en.wikipedia.org/wiki/MIPS_architecture_processors

官方网站:https://www.mips.com/

https://www.mips.com/?do-download=arm-to-mips-architecture-migration-guide

《4KcProgMan.pdf》

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英国科学家 Dominic Sweetman(经典著作 See MIPS Run 的作者),称 MIPS 为“高效的 RISC 体系结构中最优雅的一种体系结构”。 它是一个双关语: 即是 Microcomputer without Interlocked Pipeline Stages 的缩写,同时又是 Millions of Instructions Per Second 的缩 写。 MIPS 的处理单元是一个五级流水线:Instruction Fetch, Register & Decoder, ALU, Memory 以及 Write back。一开始的 MIPS 是为 32 位系统设计的,实际上,后续的 64 位扩 展,也依然对 32 位的工作模式向下兼容着。一如其他的 RISC 处理器,MIPS 的每条指令长度 是固定的 32bit。(因此,最长的局部跳转指令只能跳转 2 的 26 次方 Byte,也就是 2 的 24 次 方,16777216 条指令) MIPS 有 32 个通用寄存器,编程者可以使用其中除$0 外的所有寄存器暂存数据。$0 寄存 器,在硬件上被设计为永远读出 0。我们可以用$0 寄存器的此特性,实现一些技巧性的编程, 譬如实现 NOP 操作。MIPS 本没有 NOP 指令,但由于对$0 寄存器的写入实际上无意义,可以 作为空操作使用。 事实上,编译器从高级语言(典型如 C/C++)转换为 MIPS 汇编指令时,一般总是遵守一 定的寄存器使用约定。某些寄存器用来从函数中传入和传出参数,存储临时数据,另一些则起特 殊作用,如保存调用函数时的指令地址,或作为堆栈指针等。如果你使用汇编开发,理论上可以 无视这点约定,但是,一般地,遵守这个约定,与人方便,也为己方便。关于寄存器使用的约定, 以后会展开论述。 一如所有的 RISC 处理器,MIPS 没有 CISC 那样复杂多变的寻址方式,统一为 Load/Store 寻址。任何载入和存储操作,都可写为如下形式: lw $1, offset ($2) 这条指令的操作符可以为 Load 或 Store,一次 Load/Store 操作的范围可以为字/半字/ 字节(对应 gcc 的 int, short 和 char)。偏移量是一个带符号的 16bit 整数。两个作为操作数 的寄存器可以是任何通用寄存器。(你可以向$0 写入,但无任何意义,等同于空操作)。对于 64 位模式下,也可以对 double 类型进行操作。注意 Load/Store 都必须对应一个对齐的地址,否 则会引发一个异常(Exception)。 MIPS 支持最多 4 个协处理器。协处理器 CP0 为 CPU 的控制协处理器,是体系结构中必须 实现的。CP1 为浮点处理器。CP2 保留,各生产厂商往往用来实现一些自己的特色功能,例如 RMI 的 Fast Message Ring 等。CP3 原本也是保留共扩展用,但很多 MIPS III 和 MIPS IV 时代的扩展指令集使用了它。对于 CP0,我们会有专门的一段用来讨论。 为适应处理器向多核时代的演进, MIPS 引入了多核操作必要的原子指令 (Atomic operation)、内存屏障(Barrier)等操作。在 SMP 或 AMP 等多核架构中,这些指令是并行计算 同步的保障。

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