![](https://img-blog.csdnimg.cn/20201014180756738.png?x-oss-process=image/resize,m_fixed,h_64,w_64)
xilinx
JHLLHW
这个作者很懒,什么都没留下…
展开
-
vivado软件export hardware 时报错[common 17-69]command failed:the current design is not impelent.
[common 17-69] not impelent.原创 2023-10-08 09:03:19 · 738 阅读 · 2 评论 -
[BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_
vivado run_sythesis 时出错 [BD 41-758]原创 2023-10-07 17:24:44 · 1455 阅读 · 1 评论