[BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_

 在vivado——2019中创建Create Block Design完成后运行Run Synthesis时提示

[BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK的解决办法。

检查自己的连线明明是对的，可是依旧提示错误，按照下面步骤来一遍吧！

以下步骤全部都是右击DB模块开始吧！亲测可行。

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