GHDL+gtkwave

前言

之前https://blog.csdn.net/wxkhturfun/article/details/110822618，链接中提到如何使用iverilog+gtkwave开源仿真软件来进行verilog代码的仿真，使用iverilog还可以将verilog转换为VHDL。但是遗憾是iverilog对VHDL并不怎么支持，所以本章介绍如何使用GVHD+gtkwave来进行仿真，gGVHD可在windows、Linux、Mac下运行，本文依旧是Linux

0.开放式实验CPU

这本书有点老了，但是还可以看，里面是用VHDL写的，我没有找到源码，索性把书中的源码敲了一遍，最后用GHDL仿真，写了个不太完美的testbench:https://download.csdn.net/download/wxkhturfun/28153188

1.GVHD安装

sudo apt-get install ghdl

2.VHDL举例

ADD.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity ADD is 
port (A,B:in bit;
        SUM,CARRY:out bit);
end entity ADD;
architecture behave of  ADD is
    begin
        SUM <=A xor B;
        CARRY <= A and B;
    end behave;

tb.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity tb is
    end tb;
architecture beh of tb is   
    signal a_tb,b_tb,sum_tb,carry_tb: bit;
    constant period : TIME := 10 ns;
    component ADD
       port (A,B:in bit;
        SUM,CARRY:out bit);
        end component;
    begin
    U0: ADD port map(
        A=>a_tb,
        B=>b_tb,
        SUM=>sum_tb,
        CARRY=>carry_tb
    );
    tb: process
        --constant period : time :=20ns;
        begin
            a_tb <= '0';
            b_tb <= '1';
            wait for period;
        assert ((sum_tb = '1')and (carry_tb = '0'))
            report "Test failed" severity error;
        a_tb <='1';
        b_tb <='1';
        wait for period;
        assert ((sum_tb = '0')and (carry_tb = '1'))
            report "Test failed" severity error;
        wait;
        end process;
    end beh;

3.使用gvhd仿真

2中给出了ADD.vhd，以及相应的testbench：tb.vhd，下面对其进行仿真
test.sh:

rm -rf *.vcd *.cf
 ghdl -a tb.vhd ADD.vhd

 ghdl -e tb

 ghdl -r tb --vcd=tb.vcd

 gtkwave tb.vcd

执行：./test.sh命令即可显示波形

4.后记

terminal里输入man ghdl会显示以下信息

Basic commands:

       -a     Analysis, i.e. ghdl -a file.vhdl

       -e     Elabortation, i.e. ghdl -e unit_name

       -r     Run: run the simulation, i.e. ghdl -r unit_name

       -s     Syntax-check, i.e. ghdl -s file.vhdl

       --clean
              Clean: remove generated files, i.e. ghdl --clean

       -h, --help
              Help, i.e. ghdl --help

       --version
              Version, i.e. ghdl --version

       Basic options:

       --work=NAME
              Name of the WORK library, i.e.  ghdl -a --work=foo foo.vhdl

       --std=STD
              Which VHDL standard (87|93|93c|00|02), i.e. ghdl -a --std=87 old.vhdl

       --ieee=VER
              Which IEEE library (none|standard|synopsys|mentor), i.e. ghdl -a --ieee=synopsys broken.vhdl

       --no-vital-checks
              Disable VITAL restriction checking, i.e. ghdl -a --no-vital-checks unsupported_vital.vhdl

       There are many more modes and options; please consult the documentation.

       Executables created by GHDL have addition simulation options. The most important ones are listed below:

       --help Show options for simulation and execution.

       --assert-level=LEVEL
              Assert level at which to stop simulation (none|note|warning|error|failure), i.e.  ./touchy_design
              --assert-level=note

       --stop-time=TIME
              Stop simuation after TIME, i.e. ./design --stop-time=50ns

       --vcd=FILENAME
              Dump  VCD  to  FILENAME  (a  waveform  dump, viewable with--for instance--gtkwave), i.e. ./design
              --vcd=design.vcd

       --sdf=[TYPE=]PATH=FILENAME
              Back annotate SDF onto design using TYPE (min|typ|max), instance PATH,  and  SDF  file  FILENAME,
              i.e. ./sdf_design --sdf=typ=top/inst=inst.sdf

gvhd的报错信息还是很详细的。
vhdl学习网站：http://esd.cs.ucr.edu/labs/tutorial/
参考链接：https://zhuanlan.zhihu.com/p/28970767

5. VHDL——function

摘自：https://blog.csdn.net/weixin_42255916/article/details/86509304

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY max21 IS
PORT(a,b: IN INTEGER RANGE 0 TO 15;
q: OUT INTEGER RANGE 0 TO 15);
END ENTITY;

ARCHITECTURE behave OF max21 IS
BEGIN
PROCESS(a,b)
FUNCTION max(a,b: INTEGER RANGE 0 TO 15) RETURN INTEGER IS
VARIABLE temp:INTEGER RANGE 0 TO 15;
BEGIN
IF a > b THEN
temp := a;
ELSE
temp := b;
END IF;
RETURN (temp);
END max;
BEGIN
q <= max(a,b);
END PROCESS;
END behave;