AM64X EVM 使用CCS 启动问题记录

最新推荐文章于 2024-10-16 22:28:24 发布
最新推荐文章于 2024-10-16 22:28:24 发布
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本文链接：https://blog.csdn.net/wzx_numberone/article/details/129971591
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在OSPIBOOTMODE下，开发板启动后会执行NULLBootloader，允许成功调试非A53核上的程序。在NOBOOT模式下，通过CCSScripting和load_dmsc.js脚本初始化SOC。这个过程中涉及了对多个PLL（如MainPLL,PeripheralPLL,MCUPLL等）和HSDIV的配置，以及对R5FATCM内存的填充和调试设置。在Cortex-M3中，详细展示了PLL和HSDIV的配置过程，包括设置分频器、时钟输出等。最后，提到DDR初始化过程，指出在R5和A53上执行的不同情况。
摘要由CSDN通过智能技术生成

问题记录：
在OSPI BOOT MODE下，开发板上电后会自动执行NULL Bootloader,在这种情况下能成功Debug非A53核上的程序。

在NO BOOT模式下，使用CCS Scripting初始化SOC
在这里插入图片描述
在Scripting Console运行js:

loadJSFile "C:/ti/mcu_plus_sdk_{soc}_{sdk version}/tools/ccs_load/am64x/load_dmsc.js"

在这种情况下初始化SOC,debug A53不会报错

Scripting Clone:

js:> loadJSFile "C:\ti\mcu_plus_sdk_am64x_08_05_00_24\tools\ccs_load\am64x\load_dmsc.js"
Connecting to DMSC_Cortex_M3_0!
Fill R5F ATCM memory...
Writing While(1) for R5F
Loading DMSC Firmware ... C:/ti/mcu_plus_sdk_am64x_08_05_00_24/source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
DMSC Firmware Load Done...
DMSC Firmware run starting now...
Connecting to MCU Cortex_R5_0!
 Main Boot Mode is 120
Running the board configuration initialization from R5!
Happy Debugging!!

CIO:

[MAIN_Cortex_R5_0_0] 
DMSC Firmware Version 8.5.3--v08.05.03 (Chill Capybar
DMSC Firmware revision 0x8
DMSC ABI revision 3.1

[SCICLIENT] ABI check PASSED 
[SCICLIENT] Board Configuration with Debug enabled ...
[SCICLIENT] Common Board Configuration PASSED 
[SCICLIENT] PM Board Configuration PASSED 
[SCICLIENT] RM Board Configuration PASSED 
[SCICLIENT] Security Board Configuration PASSED 

DMSC Firmware Version 8.5.3--v08.05.03 (Chill Capybar
DMSC Firmware revision 0x8
DMSC ABI revision 3.1

All tests have passed!!

Console:

DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to    [0x6000_0000, 0x4000_0000].
DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
DMSC_Cortex_M3_0: GEL Output: Debugging enabled
DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
DMSC_Cortex_M3_0: GEL Output: For debugging: 
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR.
DMSC_Cortex_M3_0: GEL Output: Disabled PLL
DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC.
DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator.
DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 14
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #7
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #7 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #8
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #8 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #9
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #9 programmed.
DMSC_Cortex_M3_0: GEL Output: Selected Main Domain PLL Controller.
DMSC_Cortex_M3_0: GEL Output: Cleared bit 0 in the PLL controller control register.
DMSC_Cortex_M3_0: GEL Output: Cleared bit 5 in the PLL Controller control register.
DMSC_Cortex_M3_0: GEL Output: PLL controller is now in bypass mode.
DMSC_Cortex_M3_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller.
DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1).
DMSC_Cortex_M3_0: GEL Output: addr: 0x80410124 = 0x00008000
DMSC_Cortex_M3_0: GEL Output: Clear GOSET.
DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear.
DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1).
DMSC_Cortex_M3_0: GEL Output: Set ALN1.
DMSC_Cortex_M3_0: GEL Output: addr: 0x80410104 = 0x00000012
DMSC_Cortex_M3_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller.
DMSC_Cortex_M3_0: GEL Output: addr: 0x80410148 = 0x00000002
DMSC_Cortex_M3_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1).
DMSC_Cortex_M3_0: GEL Output: Set GOSET to 1.
DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear.
DMSC_Cortex_M3_0: GEL Output: Enable PLL Controller (write to bit 0 in control register).
DMSC_Cortex_M3_0: GEL Output: Set GOSET to 0.
DMSC_Cortex_M3_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free.
DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register.
DMSC_Cortex_M3_0: GEL Output: PLL is locked.
DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x0000007F
DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x0000007F
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 7
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
DMSC_Cortex_M3_0: GEL Output: For debugging: 
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR.
DMSC_Cortex_M3_0: GEL Output: Disabled PLL
DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC.
DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator.
DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 9
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 79
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 15
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed.
DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register.
DMSC_Cortex_M3_0: GEL Output: PLL is locked.
DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x000003FF
DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x000003FF
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 10
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
DMSC_Cortex_M3_0: GEL Output: For debugging: 
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR.
DMSC_Cortex_M3_0: GEL Output: Disabled PLL
DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC.
DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator.
DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1
DMSC_Cortex_M3_0: GEL Output: i: 1, HSDIV value is -1, don't program this one
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output disabled.
DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 8
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 17
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #5
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #5 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #6
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 7
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #6 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #7
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 17
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #7 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #8
DMSC_Cortex_M3_0: GEL Output: i: 8, HSDIV value is -1, don't program this one
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output disabled.
DMSC_Cortex_M3_0: GEL Output: HSDIV #8 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #9
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 4
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #9 programmed.
DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register.
DMSC_Cortex_M3_0: GEL Output: PLL is locked.
DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001
DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000001
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 1
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
DMSC_Cortex_M3_0: GEL Output: For debugging: 
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000008
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00008000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR.
DMSC_Cortex_M3_0: GEL Output: Disabled PLL
DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC.
DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator.
DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 1
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed.
DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register.
DMSC_Cortex_M3_0: GEL Output: PLL is locked.
DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000001
DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000001
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 1
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
DMSC_Cortex_M3_0: GEL Output: For debugging: 
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000C
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000C000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR.
DMSC_Cortex_M3_0: GEL Output: Disabled PLL
DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC.
DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator.
DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 3
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed.
DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register.
DMSC_Cortex_M3_0: GEL Output: PLL is locked.
DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x00000003
DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x00000003
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 2
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
DMSC_Cortex_M3_0: GEL Output: For debugging: 
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000E
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000E000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR.
DMSC_Cortex_M3_0: GEL Output: Disabled PLL
DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC.
DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator.
DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 2
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed.
DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register.
DMSC_Cortex_M3_0: GEL Output: PLL is locked.
DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: Unlocked PLL MMRs.
DMSC_Cortex_M3_0: GEL Output: Read configuration MMRs.
DMSC_Cortex_M3_0: GEL Output: temp value (HSDIV_Presence) = 0x0000001F
DMSC_Cortex_M3_0: GEL Output: HSDIV presence value = 0x0000001F
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 5
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Note: deskew PLL programming isn't implemented yet
DMSC_Cortex_M3_0: GEL Output: This is a fractional PLL, continuing on with normal programming.
DMSC_Cortex_M3_0: GEL Output: For debugging: 
DMSC_Cortex_M3_0: GEL Output: Base address: 0x04040000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Clocking scheme: 1
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass via Control MMR.
DMSC_Cortex_M3_0: GEL Output: Disabled PLL
DMSC_Cortex_M3_0: GEL Output: Enabled noise-cancelling DAC.
DMSC_Cortex_M3_0: GEL Output: Enabled the Delta-Sigma modulator.
DMSC_Cortex_M3_0: GEL Output: Programmed Reference clock pre-divider in output clock divider register.
DMSC_Cortex_M3_0: GEL Output: Programmed the integer feedback divider value in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Fractional Divider Value is -1, don't set the fractional divider.
DMSC_Cortex_M3_0: GEL Output: Programmed the fractional feedback divider in Freq Control 0 register.
DMSC_Cortex_M3_0: GEL Output: Disabled the 4-phase clock generator (clk_4ph_en) in the control register.
DMSC_Cortex_M3_0: GEL Output: Enabled the FOUT4PHASE clocks in the control register.
DMSC_Cortex_M3_0: GEL Output: Set the first post-divider value (POSTDIV1) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Set the second post-divider value (POSTDIV2) in the output divider control register.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #0
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 5
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #0 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #1
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #1 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #2
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 24
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #2 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #3
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #3 programmed.
DMSC_Cortex_M3_0: GEL Output: Programming HSDIV #4
DMSC_Cortex_M3_0: GEL Output: hsdiv_value: 11
DMSC_Cortex_M3_0: GEL Output: HSDIV reset asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV divider value programmed.
DMSC_Cortex_M3_0: GEL Output: HSDIV clock output enabled. Reset automatically de-asserted.
DMSC_Cortex_M3_0: GEL Output: HSDIV reset de-asserted
DMSC_Cortex_M3_0: GEL Output: HSDIV #4 programmed.
DMSC_Cortex_M3_0: GEL Output: Selected MCU Domain PLL Conntroller.
DMSC_Cortex_M3_0: GEL Output: Cleared bit 0 in the PLL controller control register.
DMSC_Cortex_M3_0: GEL Output: Cleared bit 5 in the PLL Controller control register.
DMSC_Cortex_M3_0: GEL Output: PLL controller is now in bypass mode.
DMSC_Cortex_M3_0: GEL Output: Set reset isolation to prevent a warm reset from killing the PLL controller.
DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1).
DMSC_Cortex_M3_0: GEL Output: addr: 0x84020124 = 0x00008000
DMSC_Cortex_M3_0: GEL Output: Clear GOSET.
DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear.
DMSC_Cortex_M3_0: GEL Output: Set PLLDIV1 (output_div1).
DMSC_Cortex_M3_0: GEL Output: Set ALN1.
DMSC_Cortex_M3_0: GEL Output: addr: 0x84020104 = 0x00000012
DMSC_Cortex_M3_0: GEL Output: Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller.
DMSC_Cortex_M3_0: GEL Output: addr: 0x84020148 = 0x00000002
DMSC_Cortex_M3_0: GEL Output: Set the clock control register to enable the OBSCLK output (bit 1).
DMSC_Cortex_M3_0: GEL Output: Set GOSET to 1.
DMSC_Cortex_M3_0: GEL Output: GOSTAT is clear.
DMSC_Cortex_M3_0: GEL Output: Enable PLL Controller (write to bit 0 in control register).
DMSC_Cortex_M3_0: GEL Output: Set GOSET to 0.
DMSC_Cortex_M3_0: GEL Output: PLLCTRL reset is cleared. PLLCTRL is free.
DMSC_Cortex_M3_0: GEL Output: Set the enable bit in the control register.
DMSC_Cortex_M3_0: GEL Output: PLL is locked.
DMSC_Cortex_M3_0: GEL Output: External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC.
DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals...
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0_PBIST
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0 done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0 done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1 done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done. 
DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done. 
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals. 
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done. 
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F. 
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done. 
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done. 
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output: 
DMSC_Cortex_M3_0: GEL Output: *****DDR is configured using R5 or A53 GELs
DMSC_Cortex_M3_0: GEL Output: M4F WFI Vector set into IRAM.
MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output: 

DDR not initialized with R5 connect.

Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.

//when connect R5,error:
AM64_DDR_Initialization_ECC_Disabled() cannot be evaluated.
Could not read 0x0F30A14C: target is not connected
	 at (*((unsigned int*) ((AM64_DDRSS_CTL_BASE+0x2000)+0x14c))&0x1) [AM64_DDRSS_Config.gel:123]
	 at AM64_DDR_Initialization_ECC_Disabled()


//when connect A53:
CortexA53_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<---
CortexA53_0: GEL Output: --->>> ECC Disabled <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR controller programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PI programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
CortexA53_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
CortexA53_0: GEL Output: --->>> DDR PHY programming completed... <<<---
CortexA53_0: GEL Output: Debugging enabled
CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
CortexA53_0: GEL Output: hsdiv_value: 3
CortexA53_0: GEL Output: HSDIV reset asserted
CortexA53_0: GEL Output: HSDIV divider value programmed.
CortexA53_0: GEL Output: HSDIV reset de-asserted
CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
CortexA53_0: GEL Output: Setting DDR4 frequency...
CortexA53_0: GEL Output: Triggering start bit from PI...
CortexA53_0: GEL Output: --->>> DDR PI initialization started... <<<---
CortexA53_0: GEL Output: Triggering start bit from CTL...
CortexA53_0: GEL Output: --->>> DDR CTL initialization started... <<<---
CortexA53_0: GEL Output: Polling PI DONE bit...
CortexA53_0: GEL Output: pi_int_status = 0x29C02001...
CortexA53_0: GEL Output:  - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
CortexA53_0: GEL Output:  - PI_LVL_DONE_BIT set: The leveling operation has completed.
CortexA53_0: GEL Output:  - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
CortexA53_0: GEL Output:  - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
CortexA53_0: GEL Output:  - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
CortexA53_0: GEL Output:  - PI_VREF_DONE_BIT set: A VREF setting operation has been completed.
CortexA53_0: GEL Output:  - Not documented bit set.
CortexA53_0: GEL Output: ctl_int_status = 0x02000000...
CortexA53_0: GEL Output: --->>> DDR Initialization completed... <<<---
CortexA53_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<---
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