quartusⅡ编译时报错object “clk_out“ on left-hand side of assignment must have a net type
我在进行FPGA设计的时候遇到了这样的一个问题,找了很久也没有答案Error (10219): Verilog HDL Continuous Assignment error at divider_five.v(45): object “clk_out” on left-hand side of assignment must have a net type这是我的第45行代码assign clk_out = (cnt1 | cnt2);反复查找后依然没发现任何问题最后怀疑是他的变量类型除
原创
2021-08-30 10:31:58 ·
9688 阅读 ·
0 评论