sbc_fs65.c
/*
* Copyright 2016 - 2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file sbc_fs65.c
* @brief Driver functions for the FS65/FS45 SBC.
*
* @author nxf44615
* @version 1.0
* @date 13-Nov-2018
* @copyright Copyright 2016 - 2018 NXP
*/
/*******************************************************************************
* Includes
******************************************************************************/
#include "sbc_fs65.h"
#include "sbc_fs65_communication.h"
#include "sbc_fs65_assert.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/** @brief Shift of the register write value if secured bits are used. */
#define FS65_SECURE_WRITE_SHIFT 4U
/**
* @brief Returns true if value VAL is in the range defined by MIN and MAX values
* (range includes the border values).
* @param val Comparison value.
* @param min Minimal value of the range.
* @param max Maximal value of the range.
* @return True if value is the range. False otherwise. */
#define FS65_IS_IN_RANGE(val, min, max) (((val) >= (min)) && ((val) <= (max)))
/*******************************************************************************
* Local Functions Prototypes
******************************************************************************/
/**
* @brief Reads challenge token (next generated LFSR state) from the SBC.
*
* @param [out] wdSeed Challenge token.
* @return Status result of the function.
*/
static fs65_status_t FS65_WD_ReadChallengeToken(uint8_t* wdSeed);
/**
* @brief Compute Challenger Watchdog answer.
*
* @param token Actual LFSR value.
* @return Computed watchdog answer.
*/
static uint8_t FS65_WD_ComputeAnswer(uint8_t token);
/*******************************************************************************
* Local Variables
******************************************************************************/
/*******************************************************************************
* Local Functions - Implementation
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : FS65_WD_ReadChallengeToken
* Description : Reads challenge token (next generated LFSR state) from the SBC.
*
*END**************************************************************************/
static fs65_status_t FS65_WD_ReadChallengeToken(uint8_t* wdSeed)
{
fs65_status_t status = fs65StatusOk; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
FS_ASSERT(wdSeed != NULL);
status = FS65_ReadRegister(FS65_FS_WD_LFSR_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Store the watchdog seed from the SBC device. */
*wdSeed = response.readData;
return status;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_WD_ComputeAnswer
* Description : Compute Challenger Watchdog answer.
*
*END**************************************************************************/
static uint8_t FS65_WD_ComputeAnswer(uint8_t token)
{
uint16_t mr = token; /* Monitoring result. */
/* Compute challenger watchdog answer. */
mr *= 4U;
mr += 6U;
mr -= 4U;
mr = ~mr;
mr /= 4U;
return (uint8_t)mr;
}
/*******************************************************************************
* API - Implementation
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : FS65_Init
* Description : This function runs full initialization of the SBC device.
*
*END**************************************************************************/
fs65_status_t FS65_Init(fs65_user_config_t* userConfig)
{
fs65_status_t status = fs65StatusOk; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
fs65_current_mode_t sbcMode; /* Actual SBC mode. */
fs65_prev_mode_t prevMode; /* Previous SBC mode. */
uint8_t initIntValue;
FS_ASSERT(userConfig != NULL);
status = FS65_CheckLbistAbistOk();
if (status != fs65StatusOk)
{
return status;
}
#ifdef FS65_FEATURE_FS1B
/* Check if FS1B is at low (if implemented). */
status = FS65_CheckFS1B();
if (status != fs65StatusOk)
{
return status;
}
#endif
/* Determine if it is necessary to re-initialize main register set. */
status = FS65_GetMode(&sbcMode, &prevMode);
if (status != fs65StatusOk)
{
return status;
}
/* MSM does not have to be initialized in case of transition
* LPOFF -> NORMAL. */
if ((sbcMode == fs65ModeInit) && (prevMode != fs65PrevModeLPOFF))
{
/* Initialize main registers. */
status = FS65_WriteRegisters(userConfig->initMainRegs, userConfig->initMainRegsCount);
if (status != fs65StatusOk)
{
return fs65StatusError;
}
}
/* FSSM can be initialized only in INIT_FS. */
if (sbcMode == fs65ModeInit)
{
/* Initialize FSSM (fail-safe registers). */
status = FS65_WriteRegisters(userConfig->initFailSafeRegs, userConfig->initFailSafeRegsCount);
if (status != fs65StatusOk)
{
return fs65StatusError;
}
/* INIT_MAIN -> NORMAL_MODE. */
/* If INIT_INT config value is not defined, just read and write the register value. */
if (userConfig->initIntReg == NULL)
{
status = FS65_ReadRegister(FS65_M_INIT_INT_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
initIntValue = response.readData;
}
else
{
initIntValue = *(userConfig->initIntReg);
}
status |= FS65_WriteRegister(FS65_M_INIT_INT_ADDR, initIntValue, NULL);
if (status != fs65StatusOk)
{
return status;
}
}
/* Read Diag. registers to clear all bits. */
status = FS65_ReadRegister(FS65_M_DIAG_VPRE_ADDR, &response);
status |= FS65_ReadRegister(FS65_M_DIAG_VCORE_ADDR, &response);
status |= FS65_ReadRegister(FS65_M_DIAG_VCCA_ADDR, &response);
status |= FS65_ReadRegister(FS65_M_DIAG_VAUX_ADDR, &response);
status |= FS65_ReadRegister(FS65_M_DIAG_VSUP_VCAN_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Initialize the rest of registers. */
status = FS65_WriteRegisters(userConfig->nonInitRegs, userConfig->nonInitRegsCount);
if (status != fs65StatusOk)
{
return status;
}
/* INIT_FS -> NORMAL_WD */
status = FS65_WD_Refresh();
if (status != fs65StatusOk)
{
return status;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_WD_Refresh
* Description : Performs the watchdog refresh.
*
*END**************************************************************************/
fs65_status_t FS65_WD_Refresh(void)
{
fs65_status_t status = fs65StatusOk; /* Status variable. */
uint8_t lfsr; /* Line feed shift register for challenger WD. */
uint8_t answer; /* Calculated monitoring result. */
/* Synchronize with LFSR generator on the device. */
status = FS65_WD_ReadChallengeToken(&lfsr);
if (status != fs65StatusOk)
{
return status;
}
answer = FS65_WD_ComputeAnswer(lfsr);
status = FS65_WriteRegister(FS65_M_WD_ANSWER_ADDR,
(uint8_t)(answer << FS65_W_M_WD_ANSWER_SHIFT), NULL);
if (status != fs65StatusOk)
{
return status;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_SwitchAMUXchannel
* Description : Switches a desired channel to the AMUX pin.
*
*END**************************************************************************/
fs65_status_t FS65_SwitchAMUXchannel(fs65_amux_selection_t channelSelection)
{
/* Check of AMUX channel selection range. */
if (!FS65_IS_IN_RANGE(channelSelection, fs65AmuxVref, fs65AmuxDieTempSensor))
{
return fs65StatusError;
}
return FS65_WriteRegister(FS65_M_IO_OUT_AMUX_ADDR, (uint16_t)channelSelection, NULL);
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_SetRegulatorState
* Description : Sets state (enable/disable) of the selected voltage regulator.
*
*END**************************************************************************/
fs65_status_t FS65_SetRegulatorState(fs65_reg_mode_t vreg, bool enable)
{
fs65_status_t status; /* Status variable. */
uint8_t writeValue; /* Register write value. */
uint8_t address; /* Register address. */
uint8_t readMask; /* Register read mask. */
uint8_t writeMask; /* Register write mask. */
uint8_t writeShift; /* Register write shift. */
fs65_rx_data_t response; /* Received data. */
uint8_t secureWriteShift = FS65_SECURE_WRITE_SHIFT; /* Shift for reg. write data. */
bool readActualValue = true; /* If true, register actual value is read before write operation. */
uint8_t enableValue = enable ? 1U : 0U; /* Enable/disable regulator output. */
switch (vreg)
{
case fs65VCan:
address = FS65_M_REG_MODE_ADDR;
readMask = FS65_R_M_VCAN_EN_MASK;
writeMask = FS65_W_M_VCAN_EN_MASK;
writeShift = FS65_W_M_VCAN_EN_SHIFT;
break;
case fs65Aux:
address = FS65_M_REG_MODE_ADDR;
readMask = FS65_R_M_VAUX_EN_MASK;
writeMask = FS65_W_M_VAUX_EN_MASK;
writeShift = FS65_W_M_VAUX_EN_SHIFT;
break;
case fs65Vcca:
address = FS65_M_REG_MODE_ADDR;
readMask = FS65_R_M_VCCA_EN_MASK;
writeMask = FS65_W_M_VCCA_EN_MASK;
writeShift = FS65_W_M_VCCA_EN_SHIFT;
break;
case fs65Vcore:
address = FS65_M_REG_MODE_ADDR;
readMask = FS65_R_M_VCORE_EN_MASK;
writeMask = FS65_W_M_VCORE_EN_MASK;
writeShift = FS65_W_M_VCORE_EN_SHIFT;
break;
case fs65Vkam:
address = FS65_M_MODE_ADDR;
readMask = writeMask = FS65_RW_M_VKAM_EN_MASK;
writeShift = FS65_RW_M_VKAM_EN_SHIFT;
/* Value is not shifted for M_MODE register. */
secureWriteShift = 0;
/* Vkam bit is the only non-volatile value that can be set by M_MODE register.
* It has no sense to read content of this register before write. */
readActualValue = false;
break;
default:
return fs65StatusError;
}
if (readActualValue)
{
/* Read actual register value to preserve value of other bits. */
status = FS65_ReadRegister(address, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Compose write value. */
writeValue = FS65_BO_SETVAL((uint8_t)(response.readData << secureWriteShift),
(uint8_t)(enableValue << writeShift), writeMask);
}
else
{
/* Write just the enable/disable bit (M_MODE register only). */
writeValue = (uint8_t)(enableValue << writeShift);
}
status = FS65_WriteRegister(address, writeValue, NULL);
/* Check if the value was accepted. */
status |= FS65_ReadRegister(address, &response);
if (status != fs65StatusOk ||
(((response.readData & readMask) << secureWriteShift) != (writeValue & writeMask)))
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_GetFaultErrorCounterValue
* Description : Reads actual Fault Error Counter value.
*
*END**************************************************************************/
fs65_status_t FS65_GetFaultErrorCounterValue(uint8_t* faultErrorCounterValue)
{
fs65_status_t status; /* Status value. */
fs65_rx_data_t response; /* Register received data. */
FS_ASSERT(faultErrorCounterValue != NULL);
status = FS65_ReadRegister(FS65_M_DIAG_SF_ERR_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
*faultErrorCounterValue = FS65_BO_GET_REG_VALUE(response.readData, FS65_R_M_FLT_ERR_MASK,
FS65_R_M_FLT_ERR_SHIFT);
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_GetMode
* Description : This function gets current and previous mode of the SBC.
*
*END**************************************************************************/
fs65_status_t FS65_GetMode(fs65_current_mode_t *currentMode, fs65_prev_mode_t *prevMode)
{
fs65_status_t status = fs65StatusOk; /* Status variable. */
fs65_rx_data_t response; /* Received data. */
FS_ASSERT(currentMode != NULL);
FS_ASSERT(prevMode != NULL);
status = FS65_ReadRegister(FS65_M_MODE_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Parses response to get previous mode of the SBC. */
switch (response.readData & (FS65_R_M_LPOFF_MASK | FS65_R_M_DFS_MASK))
{
case FS65_R_M_LPOFF_RESUME_LPOFF:
*prevMode = fs65PrevModeLPOFF;
break;
case FS65_R_M_DFS_RESUME_DFS:
*prevMode = fs65PrevModeDFS;
break;
default:
*prevMode = fs65PrevModePOR;
break;
}
/* Parses response to get current mode of the SBC. */
switch (response.readData & (FS65_R_M_NORMAL_MASK | FS65_R_M_INIT_MASK))
{
case FS65_R_M_NORMAL_NORMAL:
*currentMode = fs65ModeNormal;
break;
case FS65_R_M_INIT_INIT:
*currentMode = fs65ModeInit;
break;
default:
*currentMode = fs65ModeUnknown;
break;
}
return status;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_CheckVAUX
* Description : This function checks if VAUX is safety critical and optionally
* runs related diagnostics.
*
*END**************************************************************************/
fs65_status_t FS65_CheckVAUX(void)
{
fs65_status_t status = fs65StatusOk; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
/* Check ABIST2_VAUX if necessary. */
status = FS65_ReadRegister(FS65_FS_INIT_VAUX_OVUV_IMPACT_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if (((response.readData & FS65_R_FS_VAUX_FS_OV_MASK) != FS65_R_FS_VAUX_FS_OV_NO_EFFECT)
|| ((response.readData & FS65_R_FS_VAUX_FS_UV_MASK) != FS65_R_FS_VAUX_FS_OV_NO_EFFECT))
{
/* Run ABIST2_VAUX. */
status = FS65_WriteRegister(FS65_FS_BIST_ADDR, FS65_W_FS_ABIST2_VAUX_ABIST_VAUX, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Wait for 200 us (see AN5238 document for details). */
MCU_WaitUs(200);
/* Check BIST for ABIST2_VAUX result. */
status = FS65_ReadRegister(FS65_FS_BIST_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_R_FS_ABIST2_VAUX_OK_MASK) != FS65_R_FS_ABIST2_VAUX_OK_PASS)
{
return fs65StatusError;
}
}
return status;
}
#ifdef FS65_FEATURE_FS1B
/*FUNCTION**********************************************************************
*
* Function Name : FS65_CheckFS1B
* Description : This function checks if FS1B has expected low level during
* initialization and runs related diagnostics.
*
*END**************************************************************************/
fs65_status_t FS65_CheckFS1B(void)
{
fs65_status_t status = fs65StatusOk; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
status = FS65_ReadRegister(FS65_M_DEVICE_ID_FS_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Check if FS1B is implemented. */
if ((response.readData & FS65_R_M_FS1_MASK) == FS65_R_M_FS1_ENABLE)
{
status = FS65_ReadRegister(FS65_FS_RELEASE_FSXB_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Check if FS1B is at high. */
if ((response.readData & FS65_R_FS_FS1B_SNS_MASK) == FS65_R_FS_FS1B_SNS_HIGH)
{
status = FS65_ReadRegister(FS65_M_DIAG_SF_IOS_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Check DIAG_SF_IOS for short-circuit to high. */
if (((response.readData & FS65_R_M_FS1B_DIAG_MASK) == FS65_R_M_FS1B_DIAG_SC_LOW) ||
((response.readData & FS65_R_M_FS1B_DIAG_MASK) == FS65_R_M_FS1B_DIAG_SC_HIGH))
{
return fs65StatusError;
}
}
/* Run ABIST2_FS1B. */
status = FS65_WriteRegister(FS65_FS_BIST_ADDR, FS65_W_FS_ABIST2_FS1B_ABIST_FS1B, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Wait 200 us (see AN5238 document for details). */
MCU_WaitUs(200);
/* Check BIST for ABIST2_FS1B result. */
status = FS65_ReadRegister(FS65_FS_BIST_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_R_FS_ABIST2_FS1B_OK_MASK) !=
FS65_R_FS_ABIST2_FS1B_OK_PASS)
{
return fs65StatusError;
}
}
return status;
}
#endif
/*FUNCTION**********************************************************************
*
* Function Name : FS65_ReleaseFSx
* Description : This function releases selected fail-safe output as a part of
* error recovery procedure.
*
*END**************************************************************************/
fs65_status_t FS65_ReleaseFSx(fs65_fsxb_release_t fsOutput)
{
fs65_status_t status = fs65StatusOk; /* Status variable. */
uint8_t writeData; /* Data to be written. */
uint8_t wdSeed; /* Watchdog seed value. */
FS_ASSERT((fsOutput == fs65ReleaseFs0b) || (fsOutput == fs65ReleaseFs1b) || \
(fsOutput == fs65ReleaseFs0bFs1b));
#ifdef FS65_FEATURE_FS1B
status = FS65_CheckFS1B();
if (status != fs65StatusOk)
{
return status;
}
#endif
status = FS65_CheckVAUX();
if (status != fs65StatusOk)
{
return status;
}
/* Get actual LFSR state. */
status = FS65_WD_ReadChallengeToken(&wdSeed);
if (status != fs65StatusOk)
{
return status;
}
/* Prepare release word. */
switch (fsOutput)
{
case fs65ReleaseFs0b:
writeData = (uint8_t)fs65ReleaseFs0b;
writeData |= (wdSeed & (1U << 4U) ? 0x00U : 0x01U);
writeData |= (wdSeed & (1U << 3U) ? 0x00U : 0x02U);
writeData |= (wdSeed & (1U << 2U) ? 0x00U : 0x04U);
writeData |= (wdSeed & (1U << 1U) ? 0x00U : 0x08U);
writeData |= (wdSeed & (1U << 0U) ? 0x00U : 0x10U);
break;
#ifdef FS65_FEATURE_FS1B
case fs65ReleaseFs1b:
writeData = (uint8_t)fs65ReleaseFs1b;
writeData |= (wdSeed & (1U << 7U) ? 0x00U : 0x01U);
writeData |= (wdSeed & (1U << 6U) ? 0x00U : 0x02U);
writeData |= (wdSeed & (1U << 5U) ? 0x00U : 0x04U);
writeData |= (wdSeed & (1U << 4U) ? 0x00U : 0x08U);
writeData |= (wdSeed & (1U << 3U) ? 0x00U : 0x10U);
break;
case fs65ReleaseFs0bFs1b:
writeData = (uint8_t)fs65ReleaseFs0bFs1b;
writeData |= (wdSeed & (1U << 7U) ? 0x00U : 0x01U);
writeData |= (wdSeed & (1U << 6U) ? 0x00U : 0x02U);
writeData |= (wdSeed & (1U << 2U) ? 0x00U : 0x04U);
writeData |= (wdSeed & (1U << 1U) ? 0x00U : 0x08U);
writeData |= (wdSeed & (1U << 0U) ? 0x00U : 0x10U);
break;
#endif
default:
return fs65StatusError;
}
return FS65_WriteRegister(FS65_FS_RELEASE_FSXB_ADDR, writeData, NULL);
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_CheckLbistAbistOk
* Description : Checks if the ABIST1 and LBIST diagnostics passed. If not,
* the function returns error code.
*
*END**************************************************************************/
fs65_status_t FS65_CheckLbistAbistOk(void)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
/* Check BIST for LBIST & ABIST1 completion. */
status = FS65_ReadRegister(FS65_FS_BIST_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_R_FS_ABIST1_OK_MASK) != FS65_R_FS_ABIST1_OK_PASS)
{
return fs65StatusError;
}
if ((response.readData & FS65_R_FS_LBIST_OK_MASK) != FS65_R_FS_LBIST_OK_PASS)
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_SetLowPowerMode
* Description : This function switches mode of the SBC to the LPOFF,
* optionally with automatic wake-up 1ms after transition.
*
*END**************************************************************************/
fs65_status_t FS65_SetLowPowerMode(bool autoWU)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be updated. */
/* Read VKAM control state to preserve it. */
status = FS65_ReadRegister(FS65_M_MODE_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Set previously read VKAM value to write data. */
writeData = (response.readData & FS65_RW_M_VKAM_EN_MASK) | FS65_W_M_GO_LPOFF_LPOFF;
/* Set LPOFF mode. */
writeData |= autoWU ? FS65_W_M_LPOFF_AUTO_WU_LPOFF : FS65_W_M_GO_LPOFF_LPOFF;
return FS65_WriteRegister(FS65_M_MODE_ADDR, writeData, NULL);
/* Write check is not performed because of entering LPOFF mode. */
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_RequestInterrupt
* Description : This function requests an interrupt (pulse on the INT pin).
*
*END**************************************************************************/
fs65_status_t FS65_RequestInterrupt(void)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Register write data. */
/* Prepare content. */
status = FS65_ReadRegister(FS65_M_MODE_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Save VKAM value and set INT_REQ bit. */
writeData = (response.readData & FS65_RW_M_VKAM_EN_MASK) | FS65_W_M_INT_REQ_INT_REQ;
return FS65_WriteRegister(FS65_M_MODE_ADDR, writeData, NULL);
/* Write check is not performed because written value cannot be read out. */
}
#ifdef FS65_FEATURE_CAN
/*FUNCTION**********************************************************************
*
* Function Name : FS65_CAN_SetMode
* Description : This function changes CAN mode and the automatic transition
* of the CAN transceiver to the low-power mode on specific events.
*
*END**************************************************************************/
fs65_status_t FS65_CAN_SetMode(fs65_can_mode_t mode, bool autoDis)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Read current register value. */
status = FS65_ReadRegister(FS65_M_CAN_LIN_MODE_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Update register. */
writeData = (response.readData & (FS65_RW_M_LIN_AUTO_DIS_MASK | FS65_RW_M_LIN_MODE_MASK)) |
(uint8_t)mode | (autoDis ? FS65_RW_M_CAN_AUTO_DIS_RESET : FS65_RW_M_CAN_AUTO_DIS_NO);
status = FS65_WriteRegister(FS65_M_CAN_LIN_MODE_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check written data. */
status = FS65_ReadRegister(FS65_M_CAN_LIN_MODE_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & (FS65_RW_M_CAN_AUTO_DIS_MASK | FS65_RW_M_CAN_MODE_MASK)) !=
((uint8_t)mode | (autoDis ? FS65_RW_M_CAN_AUTO_DIS_RESET : FS65_RW_M_CAN_AUTO_DIS_NO)))
{
return fs65StatusError;
}
return fs65StatusOk;
}
#endif
#ifdef FS65_FEATURE_LIN
/*FUNCTION**********************************************************************
*
* Function Name : FS65_LIN_SetMode
* Description : This function changes LIN mode and the automatic transition
* of the LIN transceiver to the low-power mode on specific events.
*
*END**************************************************************************/
fs65_status_t FS65_LIN_SetMode(fs65_lin_mode_t mode, bool autoDis)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Read current register value. */
status = FS65_ReadRegister(FS65_M_CAN_LIN_MODE_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Update register. */
writeData = (response.readData & (FS65_RW_M_CAN_AUTO_DIS_MASK | FS65_RW_M_CAN_MODE_MASK)) |
(uint8_t)mode | (autoDis ? FS65_RW_M_LIN_AUTO_DIS_RESET : FS65_RW_M_LIN_AUTO_DIS_NO);
status = FS65_WriteRegister(FS65_M_CAN_LIN_MODE_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check written data. */
status = FS65_ReadRegister(FS65_M_CAN_LIN_MODE_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & (FS65_RW_M_LIN_AUTO_DIS_MASK | FS65_RW_M_LIN_MODE_MASK)) !=
((uint8_t)mode | (autoDis ? FS65_RW_M_LIN_AUTO_DIS_RESET : FS65_RW_M_LIN_AUTO_DIS_NO)))
{
return fs65StatusError;
}
return fs65StatusOk;
}
#endif
/*******************************************************************************
* Code - public functions - LDT (long duration timer)
******************************************************************************/
#ifdef FS65_FEATURE_LDT
/*FUNCTION**********************************************************************
*
* Function Name : FS65_LDT_SetTmrOp
* Description : This function sets operating function of the LDT.
*
*END**************************************************************************/
fs65_status_t FS65_LDT_SetTimerOperation(fs65_ldt_function_t op)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Read current register value. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Update register. */
writeData = (response.readData & (FS65_RW_M_LDT_ENABLE_MASK | FS65_RW_M_MODE_MASK |
FS65_RW_M_REG_SE_MASK)) | (uint8_t)op;
status = FS65_WriteRegister(FS65_M_LONG_DURATION_TIMER_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check written data. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_RW_M_F2_F0_MASK) != (uint8_t)op)
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_LDT_SetTmrMode
* Description : This function sets mode of the LDT (normal/calibration).
*
*END**************************************************************************/
fs65_status_t FS65_LDT_SetTimerMode(fs65_ldt_mode_t mode)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Read current register value. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Update register. */
writeData = (response.readData & (FS65_RW_M_LDT_ENABLE_MASK | FS65_RW_M_REG_SE_MASK |
FS65_RW_M_F2_F0_MASK)) | (uint8_t)mode;
status = FS65_WriteRegister(FS65_M_LONG_DURATION_TIMER_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check written data. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_RW_M_MODE_MASK) != (uint8_t)mode)
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_LDT_SetWakeUpRegSrc
* Description : This function sets counter to read real-time counter or
* programmed value into wake-up register.
*
*END**************************************************************************/
fs65_status_t FS65_LDT_SetWakeUpRegSrc(fs65_ldt_wu_scr_t source)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Read current register value. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Update register. */
writeData = (response.readData & (FS65_RW_M_LDT_ENABLE_MASK | FS65_RW_M_MODE_MASK |
FS65_RW_M_F2_F0_MASK)) | (uint8_t)source;
status = FS65_WriteRegister(FS65_M_LONG_DURATION_TIMER_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check written data. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_RW_M_REG_SE_MASK) != (uint8_t)source)
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_LDT_RunCounter
* Description : This function starts or stops the LDT counter.
*
*END**************************************************************************/
fs65_status_t FS65_LDT_RunCounter(bool run)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Read current register value. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Update register. */
writeData = (response.readData & (FS65_RW_M_MODE_MASK | FS65_RW_M_REG_SE_MASK |
FS65_RW_M_F2_F0_MASK)) | (run ? FS65_RW_M_LDT_ENABLE_START : FS65_RW_M_LDT_ENABLE_STOP);
status = FS65_WriteRegister(FS65_M_LONG_DURATION_TIMER_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check written data. */
status = FS65_ReadRegister(FS65_M_LONG_DURATION_TIMER_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_RW_M_LDT_ENABLE_MASK) !=
(run ? FS65_RW_M_LDT_ENABLE_START : FS65_RW_M_LDT_ENABLE_STOP))
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_LDT_SetAfterRunValue
* Description : This function sets new after-run value for the LDT.
*
*END**************************************************************************/
fs65_status_t FS65_LDT_SetAfterRunValue(uint16_t value)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Set high byte. */
writeData = (uint8_t)((value >> 8) & 0xFFU);
status = FS65_WriteRegister(FS65_M_LDT_AFTER_RUN_1_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
status = FS65_ReadRegister(FS65_M_LDT_AFTER_RUN_1_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if (response.readData != writeData)
{
return fs65StatusError;
}
/* Set low byte. */
writeData = (uint8_t)(value & 0xFFU);
status = FS65_WriteRegister(FS65_M_LDT_AFTER_RUN_2_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
status = FS65_ReadRegister(FS65_M_LDT_AFTER_RUN_2_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if (response.readData != writeData)
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_LDT_SetWakeUpValue
* Description : This function sets new wake-up value for the LDT.
*
*END**************************************************************************/
fs65_status_t FS65_LDT_SetWakeUpValue(uint32_t value)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Set high byte. */
writeData = (uint8_t)((value >> 16) & 0xFFU);
status = FS65_WriteRegister(FS65_M_LDT_WAKE_UP_1_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
status = FS65_ReadRegister(FS65_M_LDT_WAKE_UP_1_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if (response.readData != writeData)
{
return fs65StatusError;
}
/* Set middle byte. */
writeData = (uint8_t)((value >> 8) & 0xFFU);
status = FS65_WriteRegister(FS65_M_LDT_WAKE_UP_2_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
status = FS65_ReadRegister(FS65_M_LDT_WAKE_UP_2_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if (response.readData != writeData)
{
return fs65StatusError;
}
/* Set low byte. */
writeData = (uint8_t)(value & 0xFFU);
status = FS65_WriteRegister(FS65_M_LDT_WAKE_UP_3_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
status = FS65_ReadRegister(FS65_M_LDT_WAKE_UP_3_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if (response.readData != writeData)
{
return fs65StatusError;
}
return fs65StatusOk;
}
#endif
/*******************************************************************************
* Code - public functions - safety related
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : FS65_WD_ChangeWindow
* Description : This function changes duration of watchdog window.
*
*END**************************************************************************/
fs65_status_t FS65_WD_ChangeWindow(uint8_t windowDuration)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the read command. */
FS_ASSERT((windowDuration & (~((uint8_t)FS65_W_FS_WD_WINDOW_MASK))) == 0x00);
/* Write the WD Window register. */
status = FS65_WriteRegister(FS65_FS_WD_WINDOW_ADDR, windowDuration, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check the written data. */
status = FS65_ReadRegister(FS65_FS_WD_WINDOW_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_R_FS_WD_WINDOW_MASK) != (windowDuration >> FS65_W_FS_WD_WINDOW_SHIFT))
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_WD_ChangeSeed
* Description : This function changes seed of LFSR used for watchdog.
*
*END**************************************************************************/
fs65_status_t FS65_WD_ChangeSeed(uint8_t wdSeed)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the read command. */
FS_ASSERT(wdSeed != 0U); /* This value is not allowed. */
/* Write the WD seed. */
status = FS65_WriteRegister(FS65_FS_WD_LFSR_ADDR, \
(uint8_t)(wdSeed << FS65_RW_FS_WD_LFSR_SHIFT), NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check the written WD seed. */
status = FS65_ReadRegister(FS65_FS_WD_LFSR_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & FS65_RW_FS_WD_LFSR_MASK) !=
(uint8_t)(wdSeed << FS65_RW_FS_WD_LFSR_SHIFT))
{
return fs65StatusError;
}
return fs65StatusOk;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_RequestReset
* Description : This function requests a low pulse on the RSTB (MCU reset).
*
*END**************************************************************************/
fs65_status_t FS65_RequestReset(void)
{
return FS65_WriteRegister(FS65_FS_SF_OUTPUT_REQUEST_ADDR, \
FS65_W_FS_RSTB_REQ_RSTB_REQ, NULL);
/* Write check is not performed because written value cannot be read out. */
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_RequestFSxLow
* Description : This function requests a low level on the selected fail-safe output.
*
*END**************************************************************************/
fs65_status_t FS65_RequestFSxLow(fs65_fsx_req_type_t fsxSelection)
{
return FS65_WriteRegister(FS65_FS_SF_OUTPUT_REQUEST_ADDR, (uint8_t)fsxSelection, NULL);
/* Write check is not performed because written value cannot be read out. */
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_SetOUT4
* Description : This function sets level of the IO_4 when configured
* as an output.
*
*END**************************************************************************/
fs65_status_t FS65_SetOUT4(bool level)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t writeData; /* Data to be written. */
/* Read current register data. */
status = FS65_ReadRegister(FS65_M_IO_OUT_AMUX_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
/* Prepare content. */
writeData = (response.readData & FS65_RW_M_AMUX_MASK) |
(((uint8_t) level) << FS65_RW_M_IO_OUT_4_SHIFT) | FS65_RW_M_IO_OUT_4_EN_ENABLED;
/* Update register. */
status = FS65_WriteRegister(FS65_M_IO_OUT_AMUX_ADDR, writeData, NULL);
if (status != fs65StatusOk)
{
return status;
}
/* Check written data. */
status = FS65_ReadRegister(FS65_M_IO_OUT_AMUX_ADDR, &response);
if (status != fs65StatusOk)
{
return status;
}
if ((response.readData & (FS65_RW_M_IO_OUT_4_MASK | FS65_RW_M_IO_OUT_4_EN_MASK)) !=
((((uint8_t) level) << FS65_RW_M_IO_OUT_4_SHIFT) | FS65_RW_M_IO_OUT_4_EN_ENABLED))
{
return fs65StatusError;
}
return fs65StatusOk;
}
sbc_fs65.h
/*
* Copyright 2016 - 2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file sbc_fs65.h
* @brief FS65/FS45 driver interface.
*
* @author nxf44615
* @version 1.0
* @date 13-Nov-2018
* @copyright Copyright 2016 - 2018 NXP
*/
#ifndef SBC_FS65_H__
#define SBC_FS65_H__
/*******************************************************************************
* Includes
******************************************************************************/
#include "sbc_fs65_common.h"
#include "sbc_fs65_map.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/** @brief Watchdog seed default value. */
#define FS65_WD_SEED_DEFAULT 0xB2U
/** @addtogroup EnumsDefs
* @{ */
/** @brief Voltage outputs. Can be used with function @ref FS65_SetRegulatorState(). */
typedef enum
{
/** @brief VCAN control. */
fs65VCan = FS65_R_M_VCAN_EN_SHIFT,
/** @brief VAUX control (switch off not recommended if VAUX is safety critical). */
fs65Aux = FS65_R_M_VAUX_EN_SHIFT,
/** @brief VCCA control (switch off not recommended if VCCA is safety critical). */
fs65Vcca = FS65_R_M_VCCA_EN_SHIFT,
/** @brief VCORE control (switch off not recommended if VCORE is safety critical). */
fs65Vcore = FS65_R_M_VCORE_EN_SHIFT,
/** @brief VKAM control. */
fs65Vkam = 0xFF
} fs65_reg_mode_t;
/** @brief AMUX channel selection. Can be used with function @ref FS65_SwitchAMUXchannel(). */
typedef enum
{
fs65AmuxVref = FS65_RW_M_AMUX_VREF, /**< @brief V_REF. */
fs65AmuxVsnsWide = FS65_RW_M_AMUX_VSNS_W, /**< @brief V_SNS wide range. */
fs65AmuxIO_0Wide = FS65_RW_M_AMUX_IO_0_W, /**< @brief IO_0 wide range. */
fs65AmuxIO_5Wide = FS65_RW_M_AMUX_IO_5_W, /**< @brief IO_5 wide range. */
fs65AmuxVsnsTight = FS65_RW_M_AMUX_VSNS_T, /**< @brief V_SNS tight range. */
fs65AmuxIO_0Tight = FS65_RW_M_AMUX_IO_0_T, /**< @brief IO_0 tight range. */
fs65AmuxIO_5TightDivVkam = FS65_RW_M_AMUX_IO_5_T, /**< @brief IO_5 tight range/VKAM. */
fs65AmuxDieTempSensor = FS65_RW_M_AMUX_TEMP_SENSOR, /**< @brief Die Temperature Sensor. */
} fs65_amux_selection_t;
/** @brief CAN mode. Can be used with function @ref FS65_CAN_SetMode(). */
typedef enum
{
fs65CanModeSleepNoWakeup = FS65_RW_M_CAN_MODE_SLN_WU, /**< @brief Sleep/no wake-up capability. */
fs65CanModeListenOnly = FS65_RW_M_CAN_MODE_LISTEN_ONLY, /**< @brief Listen only. */
fs65CanModeSleepWakeup = FS65_RW_M_CAN_MODE_SL_WU, /**< @brief Sleep/wake-up capability. */
fs65CanModeNormal = FS65_RW_M_CAN_MODE_NORMAL, /**< @brief Normal operation mode. */
} fs65_can_mode_t;
/** @brief LIN mode. Can be used with function @ref FS65_LIN_SetMode(). */
typedef enum
{
fs65LinModeSleepNoWakeup = FS65_RW_M_LIN_MODE_SLN_WU, /**< @brief Sleep/no wake-up capability. */
fs65LinModeListenOnly = FS65_RW_M_LIN_MODE_LISTEN_ONLY, /**< @brief Listen only. */
fs65LinModeSleepWakeup = FS65_RW_M_LIN_MODE_SL_WU, /**< @brief Sleep/wake-up capability. */
fs65LinModeNormal = FS65_RW_M_LIN_MODE_NORMAL, /**< @brief Normal operation mode. */
} fs65_lin_mode_t;
/** @brief LDT operating function. Can be used with function @ref FS65_LDT_SetTimerOperation(). */
typedef enum
{
/** @brief In normal mode count and generate flag or INT when counter reaches the after run value. */
fs65LdtFunc1 = FS65_RW_M_F2_F0_FUNCTION1,
/** @brief In normal mode count until after run value is reached, then enters in LPOFF. */
fs65LdtFunc2 = FS65_RW_M_F2_F0_FUNCTION2,
/** @brief In normal mode count until after run value is reached, then enters in LPOFF. Once in LPOFF, count until
* wake-up value is reached and wake-up. */
fs65LdtFunc3 = FS65_RW_M_F2_F0_FUNCTION3,
/** @brief In LPOFF, count until wake-up value is reached and wake-up. */
fs65LdtFunc4 = FS65_RW_M_F2_F0_FUNCTION4,
/** @brief In LPOFF, count and do not wake-up. Counter value is stored in wake-up register. */
fs65LdtFunc5 = FS65_RW_M_F2_F0_FUNCTION5,
} fs65_ldt_function_t;
/** @brief LDT mode. Can be used with function @ref FS65_LDT_SetTimerMode(). */
typedef enum
{
fs65LdtModeCalibration = FS65_RW_M_MODE_CALIBRATION, /**< @brief Calibration mode (488 us resolution). */
fs65LdtModeNormal = FS65_RW_M_MODE_NORMAL, /**< @brief Normal mode (1 s resolution). */
} fs65_ldt_mode_t;
/** @brief Wake-up register source. Can be used with function @ref FS65_LDT_SetWakeUpRegSrc(). */
typedef enum
{
/** @brief Read programmed wake-up register. */
fs65LdtWakeupProg = FS65_RW_M_REG_SE_PROGRAMMED_REG,
/** @brief Read real time counter into wake-up register (after counter is stopped with LDT_ENABLE bit). */
fs65LdtWakeupRTC = FS65_RW_M_REG_SE_RTC_REG,
} fs65_ldt_wu_scr_t;
/** @brief Fail-safe output selection for its low level request.
* Can be used with function @ref FS65_RequestFSxLow(). */
typedef enum
{
/** @brief Request FS0B assertion. */
fs65ReqFS0B = FS65_W_FS_FS0B_REQ_FS0B_REQ,
/** @brief Request FS1B assertion with tDELAY controlled by the backup delay (open S1). */
fs65ReqFS1BDelay = FS65_W_FS_FS1B_DLY_REQ_FS1B_REQ,
/** @brief Request FS1B assertion with immediate assertion, no delay. */
fs65ReqFS1B = FS65_W_FS_FS1B_REQ_FS1B_REQ,
} fs65_fsx_req_type_t;
/** @} */
/*******************************************************************************
* Global Variables
******************************************************************************/
/*******************************************************************************
* API
******************************************************************************/
/** @defgroup API Driver API
* @{ */
/**
* @brief This function runs full initialization of the SBC device.
*
* This function writes configuration values to selected SBC registers
* (i.e. content of the userConfig structure),
* checks results of built-in self-test diagnostics and optionally
* runs additional procedures to ensure correct functionality of
* safety critical features.
* The first watchdog refresh is part of the initialization procedure,
* the SBC should be in NORMAL mode upon the function exit.
*
* @param userConfig Configuration structure of the SW driver.
*
* @return @ref fs65_status_t Status return code.
*
* @remark Note that main register set is initialized only after power on reset.
* It retains its values after transition to low-power mode and
* back to normal.
* It is recommended to read-out wake-up sources and diagnostic statuses
* after initialization to clear all flags.
*/
fs65_status_t FS65_Init(fs65_user_config_t* userConfig);
/**
* @brief Changes seed of LFSR used for watchdog.
*
* The watchdog seed can be changed just during the INIT_FS phase (for challenger WD)
* or during the OPEN watchdog window (for simple WD). Timing is up to the application!
*
* @param [in] wdSeed Watchdog LFSR seed.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_WD_ChangeSeed(uint8_t wdSeed);
/**
* @brief Switches a desired channel to the AMUX pin.
*
* @param [in] channelSelection Selected channel to be delivered to AMUX pin.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_SwitchAMUXchannel(fs65_amux_selection_t channelSelection);
/**
* @brief Sets state (enable/disable) of the selected voltage regulator.
*
* @param [in] vreg Voltage regulator enum (VCAN, VAUX, VCCA, VCORE).
* @param [in] enable State (enable = true / disable = false).
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_SetRegulatorState(fs65_reg_mode_t vreg, bool enable);
/**
* @brief Reads actual Fault Error Counter value.
* @param [out] faultErrorCounterValue Fault Error counter value storage.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_GetFaultErrorCounterValue(uint8_t* faultErrorCounterValue);
/**
* @brief This function gets current and previous mode of the SBC.
*
* @param [out] currentMode Current mode of the SBC device.
* @param [out] prevMode Previous mode of the SBC device.
*
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_GetMode(fs65_current_mode_t *currentMode, fs65_prev_mode_t *prevMode);
/**
* @brief This function checks if VAUX is safety critical and optionally
* runs related diagnostics.
*
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_CheckVAUX(void);
#ifdef FS65_FEATURE_FS1B
/**
* @brief This function checks if FS1B has expected low level during
* initialization and runs related diagnostics.
*
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_CheckFS1B(void);
#endif
/**
* @brief This function releases selected fail-safe output as a part of
* error recovery procedure.
*
* @param [in] fsOutput Selection of fail-safe output.
* @return @ref fs65_status_t Status return code.
*
* @remark When a fault is removed and the fault error counter changes back to
* level '0', a right word must be filled in the RELEASE_FSxB register.
* The value depends on the current WD_LFSR. LSB, MSB must be swapped,
* and a negative operation per bit must be applied.
* The RELEASE_FSxB write command must be done after the WD_LFSR read
* command within the same WD period.
*/
fs65_status_t FS65_ReleaseFSx(fs65_fsxb_release_t fsOutput);
/**
* @brief Checks if LBIST and ABIST1 diagnostics passed.
*
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_CheckLbistAbistOk(void);
/**
* @brief This function switches mode of the SBC to the LPOFF, optionally with
* automatic wake-up 1ms after transition.
*
* @param autoWU Automatic wake-up 1 ms after transition.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_SetLowPowerMode(bool autoWU);
/**
* @brief This function requests an interrupt (pulse on the INT pin).
*
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_RequestInterrupt(void);
#ifdef FS65_FEATURE_CAN
/**
* @brief This function changes CAN mode and the automatic transition of the CAN
* transceiver to the low-power mode on specific events.
*
* @param [in] mode CAN mode.
* @param [in] autoDis Automatic transition to the LPOFF on
* (CAN OT/TXD dominant/RXD recessive).
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_CAN_SetMode(fs65_can_mode_t mode, bool autoDis);
#endif
#ifdef FS65_FEATURE_LIN
/**
* @brief This function changes LIN mode and the automatic transition of the LIN
* transceiver to the low-power mode on specific events.
*
* @param [in] mode LIN mode.
* @param [in] autoDis Automatic transition to the LPOFF on
* (LIN OT/TXDL dominant/RXDL recessive).
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_LIN_SetMode(fs65_lin_mode_t mode, bool autoDis);
#endif
#ifdef FS65_FEATURE_LDT
/**
* @brief This function sets operating function of the LDT.
*
* @param [in] op Operating function of the LDT.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_LDT_SetTimerOperation(fs65_ldt_function_t op);
/**
* @brief This function sets mode of the LDT (normal/calibration).
*
* @param [in] mode Mode of the LDT.
* @return @ref fs65_status_t Status return code.
*
* @remark Resolution is 1s for normal mode and 488us for calibration mode.
*/
fs65_status_t FS65_LDT_SetTimerMode(fs65_ldt_mode_t mode);
/**
* @brief This function sets counter to read real-time counter or programmed
* value into wake-up register.
*
* @param [in] source Source for the wake-up register.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_LDT_SetWakeUpRegSrc(fs65_ldt_wu_scr_t source);
/**
* @brief This function starts or stops the LDT counter.
*
* @param [in] run Use true for start or false for stop the LDT counter.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_LDT_RunCounter(bool run);
/**
* @brief This function sets new after-run value for the LDT.
*
* @param [in] value After-run value.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_LDT_SetAfterRunValue(uint16_t value);
/**
* @brief This function sets new wake-up value for the LDT.
*
* @param [in] value Wake-up value (1 - 16777215).
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_LDT_SetWakeUpValue(uint32_t value);
#endif
/**
* @brief This function changes duration of watchdog window.
*
* @param [in] windowDuration Watchdog window duration. Use any FS65_W_FS_WD_WINDOW_*
* macro from @ref sbc_fs65_map.h.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_WD_ChangeWindow(uint8_t windowDuration);
/**
* @brief This function refreshes watchdog of the SBC device.
*
* @return @ref fs65_status_t Status return code.
*
* @remark MCU internally computes monitoring result based on a received
* challenge token (LFSR state) and sends it back as an answer.
*/
fs65_status_t FS65_WD_Refresh(void);
/**
* @brief This function requests a low pulse on the RSTB (MCU reset).
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_RequestReset(void);
/**
* @brief This function requests a low level on the selected fail-safe output.
*
* @param [in] fsxSelection Selection of fail-safe output.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_RequestFSxLow(fs65_fsx_req_type_t fsxSelection);
/**
* @brief This function sets level of the IO_4 when configured as an output.
*
* @param [in] level Level of IO_4 when configured as output. True for high
* level, false for low level.
* @return @ref fs65_status_t Status return code.
*
* @remark Note that this function automatically enables IO_4 to be used as output.
*/
fs65_status_t FS65_SetOUT4(bool level);
/** @} */
#endif /* SBC_FS65_H__ */
sbc_fs65_assert.h
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file sbc_fs65_assert.h
* @brief Assertion macro definition, for debugging purposes.
*
* @author nxf44615
* @version 1.0
* @date 13-Nov-2018
* @copyright Copyright 2016 - 2018 NXP
*/
#ifndef SBC_FS65_ASSERT_H_
#define SBC_FS65_ASSERT_H_
#include <stdbool.h>
/** @note MISRA-C:2012 violations
*
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro is defined to be used by drivers to validate input parameters and can be disabled.
*
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* The macros are used to validate input parameters to driver functions.
*
*/
/** @note Error detection and reporting
FS65 driver can use a mechanism to validate data coming from upper software layers (application code) by performing
a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on
runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important
to use this mechanism during development.
The validation is performed by using FS_ASSERT macro.
A default implementation of this macro is provided in this file. However, application developers can provide their own
implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the
project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h")
The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol:
- When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation
performed by the FS_ASSERT macro is enabled, and a failed validation triggers an infinite loop.
This configuration is recommended for development environments, as it prevents further execution and allows investigating
potential problems from the point of error detection.
- When DEV_ERROR_DETECT symbol is not defined, the FS_ASSERT macro is implemented as no-op, therefore disabling all validations.
This configuration can be used to eliminate the overhead of development-time checks.
It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to
disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks
in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point
to the file containing the custom implementation.
*/
#if defined CUSTOM_DEVASSERT
/* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */
#include "custom_devassert.h"
#elif defined (DEV_ERROR_DETECT)
/* Implement default assert macro */
static inline void FsDevAssert(volatile bool x)
{
if(x) { } else { for(;;) {} }
}
#define FS_ASSERT(x) FsDevAssert(x)
#else
/* Assert macro does nothing */
#define FS_ASSERT(x) ((void)0)
#endif
#endif /* SBC_FS65_ASSERT_H_ */
sbc_fs65_common.h
/*
* Copyright 2016 - 2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file sbc_fs65_common.h
* @brief Driver common structures, enums, macros and configuration values.
*
* This header file also contains prototypes of functions that have to be
* implemented by the user application (MCU_ prefix).
*
* @author nxf44615
* @version 1.0
* @date 13-Nov-2018
* @copyright Copyright 2016 - 2018 NXP
*/
#ifndef SBC_FS65_COMMON_H__
#define SBC_FS65_COMMON_H__
/*******************************************************************************
* Includes
******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/** @defgroup Features Defines for SBC features
*
* @note If some feature is not supported by the SBC, it can be disabled by
* the particular define renaming/deletion.
* @{ */
/** @brief FS1B functionality. */
#define FS65_FEATURE_FS1B
/** @brief CAN functionality */
#define FS65_FEATURE_CAN
/** @brief LIN functionality */
#define FS65_FEATURE_LIN
/** @brief LDT functionality */
#define FS65_FEATURE_LDT
/** @}*/
/** @defgroup EnumsDefs Enums definition
* @{ */
/** @brief FSxb pin release options. */
typedef enum
{
fs65ReleaseFs0b = 0x60, /**< @brief Release FS0b pin only. */
fs65ReleaseFs1b = 0xC0, /**< @brief Release FS1b pin only. */
fs65ReleaseFs0bFs1b = 0xA0 /**< @brief Release both FS0b and FS1b pins. */
} fs65_fsxb_release_t;
/** @name Enums related to functions used to handle SBC mode. */
/** @{*/
/** @brief Previous SBC state. */
typedef enum
{
fs65PrevModePOR, /**< @brief Previous SBC mode was POR (power on reset). */
fs65PrevModeDFS, /**< @brief Resume from deep fail-safe mode. */
fs65PrevModeLPOFF /**< @brief Resume from LPOFF mode. */
} fs65_prev_mode_t;
/** @brief Actual SBC state. */
typedef enum
{
fs65ModeUnknown, /**< @brief Current SBC mode is unknown. */
fs65ModeInit, /**< @brief Current SBC mode is INIT. */
fs65ModeNormal /**< @brief Current SBC mode is NORMAL. */
} fs65_current_mode_t;
/** @}*/
/** @brief Status return codes. */
typedef enum
{
fs65StatusOk = 0U, /**< @brief No error. */
fs65StatusError = 1U /**< @brief Error. */
} fs65_status_t;
/** @brief Command type. */
typedef enum
{
fs65RegRead, /**< @brief Register Read */
fs65RegWrite /**< @brief Register Write */
} fs65_command_t;
/** @brief Parity type. */
typedef enum
{
fs65ParityOdd, /**< @brief Number of 1s is odd. */
fs65ParityEven, /**< @brief Number of 1s is even. */
} fs65_parity_t;
/** @} */
/** @defgroup StructDefs Struct definitions
* @{ */
/** @brief Structure representing transmit data frame. */
typedef struct
{
/** @brief Main/Fail Safe register selection. */
bool isFailSafe;
/** @brief true if the SPI command is secured. */
bool isSecured;
/** @brief Register address. */
uint8_t registerAddress;
/** @brief Command type (R/W). */
fs65_command_t commandType;
/** @brief Data to be written to the register.
*
* If commandType is "read", this value will be ignored.
*/
uint8_t writeData;
} fs65_tx_data_t;
/** @brief Structure representing received data frame. */
typedef struct
{
/** @brief A device status is returned into this byte after a successful transfer. */
uint8_t deviceStatus;
/** @brief Extended diagnostics. Sent by Main or Fail-safe if secured register is accessed.
*
* Diagnostics content is saved in 4 highest bits. */
uint8_t deviceStatusEx;
/** @brief Content of a read register. */
uint8_t readData;
} fs65_rx_data_t;
/**
* @brief Structure representing configuration value of one register.
*/
typedef struct
{
uint8_t address; /**< @brief Register address */
uint8_t value; /**< @brief Value of the register. */
uint8_t readMask; /**< @brief Mask used for register read value check. */
bool isSecured; /**< @brief True if register uses secure bits. */
} fs65_reg_config_value_t;
/**
* @brief Structure for FS65 user configuration.
*
* This structure is used as a parameter for @ref FS65_Init() function.
*
* @note If any of the struct member is set to NULL (pointer values),
* such a member will be ignored and no write operation will be
* performed for this group of registers during the INIT phase.
*/
typedef struct
{
/**
* @brief INIT main registers.
*
* Array of register configuration values for INIT main registers.
* Following registers can be configured:
* - INIT_VREG
* - INIT_WU1
* - INIT_WU2
* - INIT_INH_INT
*
* @note INIT_INT register should not be present in this array as its writing causes
* transition from INIT MAIN to NORMAL MODE. INIT_INT register value can be set
* by initIntReg value (part of this structure).
*/
fs65_reg_config_value_t* initMainRegs;
uint8_t initMainRegsCount; /**< @brief Number of INIT main registers. */
/**
* @brief INIT_FS registers.
*
* Array of register configuration values for INIT FS registers.
* Following registers can be configured:
* - INIT_FS1B_TIMING
* - INIT_SUPERVISOR
* - INIT_FAULT
* - INIT_FSSM
* - INIT_SF_IMPACT
* - INIT_WD_CNT
* - INIT_VCORE_OVUV_IMPACT
* - INIT_VCCA_OVUV_IMPACT
* - INIT_VAUX_OVUV_IMPACT
*/
fs65_reg_config_value_t* initFailSafeRegs;
uint8_t initFailSafeRegsCount; /**< @brief Number of INIT_FS registers. */
/**
* @brief Non-init registers.
*
* Configuration of the rest of the registers.
*/
fs65_reg_config_value_t* nonInitRegs;
uint8_t nonInitRegsCount; /**< @brief Number of non-init registers. */
/**
* @brief Pointer to INIT_INT register value.
*
* If NULL, actual register value is read and written back.
*/
uint8_t* initIntReg;
} fs65_user_config_t;
/** @} */
/** @name Bitwise operations used by this driver. */
/** @{ */
/** @brief This macro updates value of bits specified by the mask. It is assumed that
* value is already shifted. Write value is masked also. */
#define FS65_BO_SETVAL(data, val, mask) (((data) & ~(mask)) | ((val) & (mask)))
/** @brief This macro updates value of bits specified by the mask. Additionally range
* check on the value is performed. It is assumed that value is not shifted. */
#define FS65_BO_SETVAL_EXT(data, value, mask, shift) \
(((data) & ~(mask << shift)) | (((value) & (mask)) << (shift)))
/** @brief This macro returns value specified by the mask. */
#define FS65_BO_GETVAL(data, mask, shift) ((data) & (mask) << (shift))
/**
* @brief Macro for getting value from register.
*
* @param value Value read from register.
* @param mask Bit selection.
* @param shift Bit shift.
* @returns Masked and r-shifted value. */
#define FS65_BO_GET_REG_VALUE(value, mask, shift) (((value) & (mask)) >> (shift))
/** @} */
/**
* @brief Returns true if register is fail-safe
*
* @param address Register address.
* @return true if register is fail-safe.
*/
#define FS65_IS_REG_FAILSAFE(address) ((address) & 0x20)
/*******************************************************************************
* Prototypes of extern functions
******************************************************************************/
/**
* @defgroup Extern MCU specific functions
* @attention Functions in this group must be implemented by the user.
* @{ */
/**
* @brief This function transfers single frame through blocking SPI communication
* in both directions. MCU specific.
*
* This function must be implemented if SPI communication is used.
* @warning This function must be implemented as blocking as there is not synchronization
* mechanism implemented in the driver.
* @param [in] txFrame Frame to be send.
* @param [out] rxFrame Received frame.
* @return @ref fs65_status_t Status return code. */
extern fs65_status_t MCU_SPI_TransferData(uint8_t* txFrame, uint8_t* rxFrame);
/**
* @brief This function waits for specified amount of microseconds.
*
* @param [in] delay Delay in microseconds.
*/
extern void MCU_WaitUs(uint16_t delay);
/** @} */
#endif /* SBC_FS65_COMMON_H__ */
sbc_fs65_communication.c
/*
* Copyright 2016 - 2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file sbc_fs65_communication.c
* @brief Implementation of communication logic for NXP SBC FS65/FS45.
*
* @author nxf44615
* @version 1.0
* @date 13-Nov-2018
* @copyright Copyright 2016 - 2018 NXP
*/
/*******************************************************************************
* Includes
******************************************************************************/
#include "sbc_fs65_communication.h"
#include "sbc_fs65_map.h"
#include "sbc_fs65_assert.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Data frame (SPI). */
#define FS65_REG_ADDR_MASK 0x3FU /* Register address mask (not shifted) */
#define FS65_REG_ADDR_SHIFT 0x01U /* SPI register address shift */
#define FS65_SPI_BIT_7_0 0U
#define FS65_SPI_BIT_15_8 1U
#define FS65_SPI_RW_BIT_MASK 0x80U
#define FS65_SPI_W_BIT_VALUE 0x80U
#define FS65_SPI_R_BIT_VALUE 0
#define FS65_SPI_DEVICE_STATUS_EX_MASK 0xF0U
#define FS65_SPI_FS_REGISTER_DATA_MASK 0x0FU
#define FS65_FAIL_SAFE_REGS_COUNT 14U
/*******************************************************************************
* Constants
******************************************************************************/
/**
* @brief List of secured register addresses.
*/
static const uint8_t m_securedRegisters[] = {
FS65_M_MODE_ADDR,
FS65_M_REG_MODE_ADDR,
FS65_FS_INIT_FS1B_TIMING_ADDR,
FS65_FS_BIST_ADDR,
FS65_FS_INIT_SUPERVISOR_ADDR,
FS65_FS_INIT_FAULT_ADDR,
FS65_FS_INIT_FSSM_ADDR,
FS65_FS_INIT_SF_IMPACT_ADDR,
FS65_FS_WD_WINDOW_ADDR,
FS65_FS_SF_OUTPUT_REQUEST_ADDR,
FS65_FS_INIT_WD_CNT_ADDR,
FS65_FS_INIT_VCORE_OVUV_IMPACT_ADDR,
FS65_FS_INIT_VCCA_OVUV_IMPACT_ADDR,
FS65_FS_INIT_VAUX_OVUV_IMPACT_ADDR
};
/*******************************************************************************
* Local Functions Prototypes
******************************************************************************/
/**
* @brief Returns true if register SPI transfer is secured by security bits.
*
* @param address Register address.
* @return true if register SPI transfer is secured.
*/
static inline bool FS65_IsRegisterSecured(uint8_t address);
/**
* @brief This function calculates parity value of passed data array.
* Returns 1 if the parity is even, 0 otherwise.
*
* @param data Computes parity of input data.
* @return Parity.
*/
static fs65_parity_t FS65_ComputeParity(uint16_t data);
/**
* @brief Performs SPI transfer of the txData. Received frame is saved into
* rxData structure or ignored if rxData is NULL.
*
* @param txData Data to be transmitter (MOSI).
* @param rxData Data received (MISO).
* @return @ref fs65_status_t Status return code.
*/
static fs65_status_t FS65_TransferData(fs65_tx_data_t* txData, fs65_rx_data_t* rxData);
/**
* @brief Creates a raw frame for SPI transfer.
*
* @param txData tx data.
* @param txFrame Raw frame prepared for SPI transmission (MOSI).
*/
static void FS65_CreateSendFrame(fs65_tx_data_t* txData, uint8_t* txFrame);
/**
* @brief Computes security bits from 4 MSbits and write it to 4 LSbits.
*
* @param [in, out] data
*/
static void FS65_ComputeSecurityBits(uint8_t* data);
/*******************************************************************************
* Local Variables
******************************************************************************/
/*******************************************************************************
* Local Functions - Implementation
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : FS65_IsRegisterSecured
* Description : Returns true if register SPI transfer is secured by security bits.
*
*END**************************************************************************/
static inline bool FS65_IsRegisterSecured(uint8_t address)
{
uint8_t i; /* Counter. */
for (i = 0; i < FS65_FAIL_SAFE_REGS_COUNT; i++)
{
if (address == m_securedRegisters[i])
{
return true;
}
}
return false;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_TransferData
* Description : Performs SPI transfer of the txData. Received frame is saved into
* rxData structure or ignored if rxData is NULL.
*
*END**************************************************************************/
static fs65_status_t FS65_TransferData(fs65_tx_data_t* txData, fs65_rx_data_t* rxData)
{
fs65_status_t status; /* Status variable. */
uint8_t txFrame[FS65_COMM_FRAME_SIZE_BYTES] = {0}; /* SPI Tx frame. */
uint8_t rxFrame[FS65_COMM_FRAME_SIZE_BYTES] = {0}; /* SPI Rx frame. */
FS_ASSERT(txData != NULL);
FS65_CreateSendFrame(txData, txFrame);
status = MCU_SPI_TransferData(txFrame, rxFrame);
if (status != fs65StatusOk)
{
return status;
}
if (rxData != NULL)
{
if (txData->isSecured)
{
rxData->deviceStatusEx = rxFrame[FS65_SPI_BIT_7_0] & FS65_SPI_DEVICE_STATUS_EX_MASK;
rxData->readData = rxFrame[FS65_SPI_BIT_7_0] & FS65_SPI_FS_REGISTER_DATA_MASK;
}
else
{
rxData->deviceStatusEx = 0;
rxData->readData = rxFrame[FS65_SPI_BIT_7_0];
}
rxData->deviceStatus = rxFrame[FS65_SPI_BIT_15_8];
}
return status;
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_CreateSendFrame
* Description : Creates a raw frame for SPI transfer.
*
*END**************************************************************************/
static void FS65_CreateSendFrame(fs65_tx_data_t* txData, uint8_t* txFrame)
{
fs65_parity_t parity; /* Tx frame parity result. */
FS_ASSERT(txData != NULL);
FS_ASSERT(txFrame != NULL);
txFrame[FS65_SPI_BIT_7_0] = 0;
txFrame[FS65_SPI_BIT_15_8] = 0;
/* Sets address of the register. */
txFrame[FS65_SPI_BIT_15_8] = FS65_BO_SETVAL_EXT(txFrame[FS65_SPI_BIT_15_8],
txData->registerAddress, FS65_REG_ADDR_MASK, FS65_REG_ADDR_SHIFT);
/* check if register is r or w */
switch (txData->commandType)
{
case fs65RegRead:
/* Creates read command. */
txFrame[FS65_SPI_BIT_15_8] = FS65_BO_SETVAL(txFrame[FS65_SPI_BIT_15_8],
FS65_SPI_R_BIT_VALUE, FS65_SPI_RW_BIT_MASK);
/* No data to be sent. */
txFrame[FS65_SPI_BIT_7_0] = 0x00;
break;
case fs65RegWrite:
/* Creates write command. */
txFrame[FS65_SPI_BIT_15_8] |= FS65_BO_SETVAL(txFrame[FS65_SPI_BIT_15_8],
FS65_SPI_W_BIT_VALUE, FS65_SPI_RW_BIT_MASK);
/* Sets data. */
txFrame[FS65_SPI_BIT_7_0] = txData->writeData;
if (txData->isSecured)
{
FS65_ComputeSecurityBits(&(txFrame[FS65_SPI_BIT_7_0]));
}
break;
}
/* Sets parity bit (just for the write command). */
if (txData->commandType == fs65RegWrite)
{
parity = FS65_ComputeParity((txFrame[FS65_SPI_BIT_15_8] << 8) + txFrame[FS65_SPI_BIT_7_0]);
if (parity == fs65ParityEven)
{
txFrame[FS65_SPI_BIT_15_8] = FS65_BO_SETVAL(txFrame[FS65_SPI_BIT_15_8], 1U, 1U);
}
}
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_ComputeSecurityBits
* Description : Computes security bits from 4 MSbits and write it to 4 LSbits.
*
*END**************************************************************************/
static void FS65_ComputeSecurityBits(uint8_t* data)
{
/* Set 4 LSbits to 0. */
*data &= 0xF0;
*data |= (*data & (1U << 6U) ? 1U : 0U); /* Secure 0 = Bit6 */
*data |= (*data & (1U << 7U) ? 2U : 0U); /* Secure 1 = Bit7 */
*data |= (*data & (1U << 4U) ? 0U : 4U); /* Secure 2 = NOT(Bit4) */
*data |= (*data & (1U << 5U) ? 0U : 8U); /* Secure 3 = NOT(Bit5) */
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_ComputeParity
* Description : This function calculates parity value of passed data array.
* Returns 1 if the parity is even, 0 otherwise.
*
*END**************************************************************************/
static fs65_parity_t FS65_ComputeParity(uint16_t data)
{
uint16_t x = data; /* Data from which the parity will be calculated. */
x ^= x >> 8;
x ^= x >> 4;
x ^= x >> 2;
x ^= x >> 1;
return ((~x) & 1U) ? fs65ParityEven : fs65ParityOdd;
}
/*******************************************************************************
* API - Implementation
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : FS65_ReadRegister
* Description : Performs a single read register based on provided address.
* The response is returned in @ref fs65_rx_frame_t structure.
*
*END**************************************************************************/
fs65_status_t FS65_ReadRegister(uint8_t address, fs65_rx_data_t* rxData)
{
fs65_tx_data_t txData = {
.registerAddress = address,
.commandType = fs65RegRead
};
FS_ASSERT(rxData != NULL);
/* Selects register set (main x fail-safe). */
txData.isFailSafe = FS65_IS_REG_FAILSAFE(address);
return FS65_TransferData(&txData, rxData);
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_WriteRegister
* Description : Sends write command to the FS65.
*
*END**************************************************************************/
fs65_status_t FS65_WriteRegister(uint8_t address, uint8_t writeData, fs65_rx_data_t* rxData)
{
fs65_tx_data_t txData = {
.registerAddress = address,
.writeData = writeData,
.commandType = fs65RegWrite
};
txData.isFailSafe = FS65_IS_REG_FAILSAFE(address);
txData.isSecured = FS65_IsRegisterSecured(address);
return FS65_TransferData(&txData, rxData);
}
/*FUNCTION**********************************************************************
*
* Function Name : FS65_WriteRegisters
* Description : Writes set of configuration registers values.
*
*END**************************************************************************/
fs65_status_t FS65_WriteRegisters(fs65_reg_config_value_t* registers, uint8_t numOfItems)
{
fs65_status_t status; /* Status variable. */
fs65_rx_data_t response; /* Response to the command. */
uint8_t i; /* Counter. */
fs65_reg_config_value_t* reg; /* Pointer to actually selected register configuration. */
uint8_t writeValue; /* Register write value. */
uint8_t readValue; /* Register read value. */
if (registers == NULL || numOfItems == 0)
{
return fs65StatusOk;
}
for (i = 0; i < numOfItems; i++)
{
reg = registers + i;
/* Secured registers have the write value shifted and 4 lowest bits
* are used for the Secured bits. */
writeValue = reg->isSecured ? (uint8_t)(reg->value << 4) : reg->value;
status = FS65_WriteRegister(reg->address, writeValue, NULL);
/* In case of write to the fail-safe register, add mandatory delay between
* consequent transfers (3.5 us according to the specification). */
if (FS65_IS_REG_FAILSAFE(reg->address))
{
MCU_WaitUs(4);
}
/* Check written register value. */
status |= FS65_ReadRegister(reg->address, &response);
/* Secured registers have just 4 writable bits. */
readValue = reg->isSecured ? (response.readData & 0x0F) : response.readData;
/* Read mask should be used for read value as some registers
* contains status bits, that are not writable (e.g. INIT_VREG - BAT_FAIL bit) */
if (status != fs65StatusOk || (readValue & reg->readMask) != reg->value)
{
return fs65StatusError;
}
}
return fs65StatusOk;
}
sbc_fs65_communication.h
/*
* Copyright 2016 - 2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file sbc_fs65_communication.h
* @brief This file contains functions for SPI communication.
*
* @author nxf44615
* @version 1.0
* @date 13-Nov-2018
* @copyright Copyright 2016 - 2018 NXP
*/
#ifndef SBC_FS65_COMMUNICATION_H__
#define SBC_FS65_COMMUNICATION_H__
/*******************************************************************************
* Includes
******************************************************************************/
#include "sbc_fs65_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define FS65_COMM_FRAME_SIZE_BYTES 0x02U /**< Length of the communication frame (bytes) */
/*******************************************************************************
* API
******************************************************************************/
/** @addtogroup API
* @{ */
/**
* @brief Performs a read from a single FS65 register.
*
* Performs a single read register based on provided address.
* The response is returned in @ref fs65_rx_data_t structure.
* @param [in] address Register address.
* @param [out] rxData Structure holding the response from SBC.
* @return @ref fs65_status_t Status return code. */
fs65_status_t FS65_ReadRegister(uint8_t address, fs65_rx_data_t* rxData);
/**
* @brief Sends write command to the FS65.
*
* @param [in] address Register address.
* @param [in] writeData Register write value.
* @param [out] rxData Diagnostic data returned by the SBC.
* @return @ref fs65_status_t Status return code. */
fs65_status_t FS65_WriteRegister(uint8_t address, uint8_t writeData,
fs65_rx_data_t* rxData);
/**
* Writes set of configuration registers values.
*
* If registers is NULL or numOfItems is 0, function just returns OK status code.
*
* @param [in] registers Pointer to array of register configuration values.
* @param [in] numOfItems Number of items.
* @return @ref fs65_status_t Status return code.
*/
fs65_status_t FS65_WriteRegisters(fs65_reg_config_value_t* registers, uint8_t numOfItems);
/** @} */
#endif /* SBC_FS65_COMMUNICATION_H__ */
sbc_fs65_map.h
/*
* Copyright (c) 2016 - 2018 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file sbc_fs65_map.h
* @brief Register map of the FS65/FS45 SBC series.
*
* @author nxf44615
* @version 1.0
* @date 13-Nov-2018
* @copyright Copyright 2016 - 2018 NXP
*/
#ifndef SBC_FS65_MAP_H__
#define SBC_FS65_MAP_H__
/******************************************************************************/
/* INIT_VREG - Type: RW */
/******************************************************************************/
#define FS65_M_INIT_VREG_ADDR 0x01U
#define FS65_M_INIT_VREG_DEFAULT 0x45U
/**
* Report a battery disconnection (POR of the main logic)
*/
#define FS65_R_M_BAT_FAIL_MASK 0x01U
/**
* Configure VAUX regulator as a tracker of VCCA
*/
#define FS65_RW_M_VAUX_TRK_EN_MASK 0x02U
/**
* Configure the current limitation duration before VAUX is switched off.
*/
#define FS65_RW_M_TAUX_LIM_OFF_MASK 0x04U
/**
* CAN_5V overvoltage monitoring
*/
#define FS65_RW_M_VCAN_OV_MON_MASK 0x10U
/**
* DISABLE the input power feed forward (IPFF) function of VPRE
*/
#define FS65_RW_M_IPFF_DIS_MASK 0x20U
/**
* Configure the current limitation duration before VCCA is switched off. Only available for external PNP.
*/
#define FS65_RW_M_TCCA_LIM_OFF_MASK 0x40U
/**
* Configure the current limitation threshold for VCCA. Only available for external PNP.
*/
#define FS65_RW_M_ICCA_LIM_MASK 0x80U
/**
* Report a battery disconnection (POR of the main logic)
*/
#define FS65_R_M_BAT_FAIL_SHIFT 0x00U
/**
* Configure VAUX regulator as a tracker of VCCA
*/
#define FS65_RW_M_VAUX_TRK_EN_SHIFT 0x01U
/**
* Configure the current limitation duration before VAUX is switched off.
*/
#define FS65_RW_M_TAUX_LIM_OFF_SHIFT 0x02U
/**
* CAN_5V overvoltage monitoring
*/
#define FS65_RW_M_VCAN_OV_MON_SHIFT 0x04U
/**
* DISABLE the input power feed forward (IPFF) function of VPRE
*/
#define FS65_RW_M_IPFF_DIS_SHIFT 0x05U
/**
* Configure the current limitation duration before VCCA is switched off. Only available for external PNP.
*/
#define FS65_RW_M_TCCA_LIM_OFF_SHIFT 0x06U
/**
* Configure the current limitation threshold for VCCA. Only available for external PNP.
*/
#define FS65_RW_M_ICCA_LIM_SHIFT 0x07U
/**
* NO POR
*/
#define FS65_R_M_BAT_FAIL_NO_POR (0x00U << FS65_R_M_BAT_FAIL_SHIFT)
/**
* POR occurred
*/
#define FS65_R_M_BAT_FAIL_POR (0x01U << FS65_R_M_BAT_FAIL_SHIFT)
/**
* NO tracking
*/
#define FS65_RW_M_VAUX_TRK_EN_NO_TRACKING (0x00U << FS65_RW_M_VAUX_TRK_EN_SHIFT)
/**
* Tracking mode enabled and latched
*/
#define FS65_RW_M_VAUX_TRK_EN_TRACKING (0x01U << FS65_RW_M_VAUX_TRK_EN_SHIFT)
/**
* 10 ms
*/
#define FS65_RW_M_TAUX_LIM_OFF_10_MS (0x00U << FS65_RW_M_TAUX_LIM_OFF_SHIFT)
/**
* 50 ms
*/
#define FS65_RW_M_TAUX_LIM_OFF_50_MS (0x01U << FS65_RW_M_TAUX_LIM_OFF_SHIFT)
/**
* Off. VCAN OV is not monitored. Flag is ignored.
*/
#define FS65_RW_M_VCAN_OV_MON_OFF (0x00U << FS65_RW_M_VCAN_OV_MON_SHIFT)
/**
* On. VCAN OV is monitored. If OV the CAN_5V regulator is switched off.
*/
#define FS65_RW_M_VCAN_OV_MON_ON (0x01U << FS65_RW_M_VCAN_OV_MON_SHIFT)
/**
* Enabled
*/
#define FS65_RW_M_IPFF_DIS_ENABLED (0x00U << FS65_RW_M_IPFF_DIS_SHIFT)
/**
* Disabled
*/
#define FS65_RW_M_IPFF_DIS_DISABLED (0x01U << FS65_RW_M_IPFF_DIS_SHIFT)
/**
* 10 ms
*/
#define FS65_RW_M_TCCA_LIM_OFF_10_MS (0x00U << FS65_RW_M_TCCA_LIM_OFF_SHIFT)
/**
* 50 ms
*/
#define FS65_RW_M_TCCA_LIM_OFF_50_MS (0x01U << FS65_RW_M_TCCA_LIM_OFF_SHIFT)
/**
* ICCA_LIM_OUT
*/
#define FS65_RW_M_ICCA_LIM_ICCA_LIM_OUT (0x00U << FS65_RW_M_ICCA_LIM_SHIFT)
/**
* ICCA_LIM_INT
*/
#define FS65_RW_M_ICCA_LIM_ICCA_LIM_INT (0x01U << FS65_RW_M_ICCA_LIM_SHIFT)
/******************************************************************************/
/* LONG_DURATION_TIMER - Type: RW */
/******************************************************************************/
#define FS65_M_LONG_DURATION_TIMER_ADDR 0x06U
#define FS65_M_LONG_DURATION_TIMER_DEFAULT 0x04U
/**
* Counter status
*/
#define FS65_R_M_LDT_INT_MASK 0x01U
/**
* LDT counter control
*/
#define FS65_RW_M_LDT_ENABLE_MASK 0x02U
/**
* Operating mode selection
*/
#define FS65_RW_M_MODE_MASK 0x04U
/**
* Counter status
*/
#define FS65_R_M_LDT_RUNNING_MASK 0x08U
/**
* Counter register selection
*/
#define FS65_RW_M_REG_SE_MASK 0x10U
/**
* Select timer operating function
*/
#define FS65_RW_M_F2_F0_MASK 0xE0U
/**
* Counter status
*/
#define FS65_R_M_LDT_INT_SHIFT 0x00U
/**
* LDT counter control
*/
#define FS65_RW_M_LDT_ENABLE_SHIFT 0x01U
/**
* Operating mode selection
*/
#define FS65_RW_M_MODE_SHIFT 0x02U
/**
* Counter status
*/
#define FS65_R_M_LDT_RUNNING_SHIFT 0x03U
/**
* Counter register selection
*/
#define FS65_RW_M_REG_SE_SHIFT 0x04U
/**
* Select timer operating function
*/
#define FS65_RW_M_F2_F0_SHIFT 0x05U
/**
* Counter not running
*/
#define FS65_R_M_LDT_INT_NOT_RUNNING (0x00U << FS65_R_M_LDT_INT_SHIFT)
/**
* Counter running
*/
#define FS65_R_M_LDT_INT_RUNNING (0x01U << FS65_R_M_LDT_INT_SHIFT)
/**
* LDT counter stop
*/
#define FS65_RW_M_LDT_ENABLE_STOP (0x00U << FS65_RW_M_LDT_ENABLE_SHIFT)
/**
* LDT counter start
*/
#define FS65_RW_M_LDT_ENABLE_START (0x01U << FS65_RW_M_LDT_ENABLE_SHIFT)
/**
* Calibration mode (488 us resolution)
*/
#define FS65_RW_M_MODE_CALIBRATION (0x00U << FS65_RW_M_MODE_SHIFT)
/**
* Normal mode (1 s resolution)
*/
#define FS65_RW_M_MODE_NORMAL (0x01U << FS65_RW_M_MODE_SHIFT)
/**
* Counter not running
*/
#define FS65_R_M_LDT_RUNNING_NOT_RUNNING (0x00U << FS65_R_M_LDT_RUNNING_SHIFT)
/**
* Counter running
*/
#define FS65_R_M_LDT_RUNNING_RUNNING (0x01U << FS65_R_M_LDT_RUNNING_SHIFT)
/**
* Read programmed wake-up register
*/
#define FS65_RW_M_REG_SE_PROGRAMMED_REG (0x00U << FS65_RW_M_REG_SE_SHIFT)
/**
* Read real time counter into wake-up register (after counter is stopped with LDT_ENABLE bit)
*/
#define FS65_RW_M_REG_SE_RTC_REG (0x01U << FS65_RW_M_REG_SE_SHIFT)
/**
* In normal mode count and generate flag or INT when counter reaches the after run value
*/
#define FS65_RW_M_F2_F0_FUNCTION1 (0x00U << FS65_RW_M_F2_F0_SHIFT)
/**
* In normal mode count until after run value is reached, then enters in LPOFF
*/
#define FS65_RW_M_F2_F0_FUNCTION2 (0x01U << FS65_RW_M_F2_F0_SHIFT)
/**
* In normal mode count until after run value is reached, then enters in LPOFF. Once in LPOFF, count until wake-up
* value is reached and wake-up
*/
#define FS65_RW_M_F2_F0_FUNCTION3 (0x02U << FS65_RW_M_F2_F0_SHIFT)
/**
* In LPOFF, count until wake-up value is reached and wake-up
*/
#define FS65_RW_M_F2_F0_FUNCTION4 (0x03U << FS65_RW_M_F2_F0_SHIFT)
/**
* In LPOFF, count and do not wake-up. Counter value is stored in wake-up register
*/
#define FS65_RW_M_F2_F0_FUNCTION5 (0x04U << FS65_RW_M_F2_F0_SHIFT)
/******************************************************************************/
/* HW_CONFIG - Type: R */
/******************************************************************************/
#define FS65_M_HW_CONFIG_ADDR 0x08U
#define FS65_M_HW_CONFIG_DEFAULT 0x04U
/**
* Report the configuration of the DEBUG mode
*/
#define FS65_R_M_DBG_HW_MASK 0x01U
/**
* Report the deep fail-safe hardware configuration (main logic)
*/
#define FS65_R_M_DFS_HW1_MASK 0x02U
/**
* Report the hardware configuration for VAUX
*/
#define FS65_R_M_VAUX_HW_MASK 0x08U
/**
* Report the hardware configuration for VCCA
*/
#define FS65_R_M_VCCA_HW_MASK 0x10U
/**
* Report the connection of an external PNP on VCCA
*/
#define FS65_R_M_VCCA_PNP_DET_MASK 0x20U
/**
* Report the hardware configuration of VPRE
*/
#define FS65_R_M_LS_DETECT_MASK 0x80U
/**
* Report the configuration of the DEBUG mode
*/
#define FS65_R_M_DBG_HW_SHIFT 0x00U
/**
* Report the deep fail-safe hardware configuration (main logic)
*/
#define FS65_R_M_DFS_HW1_SHIFT 0x01U
/**
* Report the hardware configuration for VAUX
*/
#define FS65_R_M_VAUX_HW_SHIFT 0x03U
/**
* Report the hardware configuration for VCCA
*/
#define FS65_R_M_VCCA_HW_SHIFT 0x04U
/**
* Report the connection of an external PNP on VCCA
*/
#define FS65_R_M_VCCA_PNP_DET_SHIFT 0x05U
/**
* Report the hardware configuration of VPRE
*/
#define FS65_R_M_LS_DETECT_SHIFT 0x07U
/**
* Normal operation
*/
#define FS65_R_M_DBG_HW_NORMAL (0x00U << FS65_R_M_DBG_HW_SHIFT)
/**
* Debug mode selected
*/
#define FS65_R_M_DBG_HW_DEBUG (0x01U << FS65_R_M_DBG_HW_SHIFT)
/**
* Deep fail-safe disable
*/
#define FS65_R_M_DFS_HW1_DISABLE (0x00U << FS65_R_M_DFS_HW1_SHIFT)
/**
* Deep fail-safe enable
*/
#define FS65_R_M_DFS_HW1_ENABLE (0x01U << FS65_R_M_DFS_HW1_SHIFT)
/**
* 5.0 V
*/
#define FS65_R_M_VAUX_HW_5_0V (0x00U << FS65_R_M_VAUX_HW_SHIFT)
/**
* 3.3 V
*/
#define FS65_R_M_VAUX_HW_3_3V (0x01U << FS65_R_M_VAUX_HW_SHIFT)
/**
* 3.3 V
*/
#define FS65_R_M_VCCA_HW_3_3V (0x00U << FS65_R_M_VCCA_HW_SHIFT)
/**
* 5.0 V
*/
#define FS65_R_M_VCCA_HW_5_0V (0x01U << FS65_R_M_VCCA_HW_SHIFT)
/**
* External PNP connected
*/
#define FS65_R_M_VCCA_PNP_DET_PNP_CONNECTED (0x00U << FS65_R_M_VCCA_PNP_DET_SHIFT)
/**
* Internal MOSFET
*/
#define FS65_R_M_VCCA_PNP_DET_INT_MOSFET (0x01U << FS65_R_M_VCCA_PNP_DET_SHIFT)
/**
* Buck-boost
*/
#define FS65_R_M_LS_DETECT_BUCK_BOOST (0x00U << FS65_R_M_LS_DETECT_SHIFT)
/**
* Buck only
*/
#define FS65_R_M_LS_DETECT_BUCK_ONLY (0x01U << FS65_R_M_LS_DETECT_SHIFT)
/******************************************************************************/
/* WU_SOURCE - Type: R */
/******************************************************************************/
#define FS65_M_WU_SOURCE_ADDR 0x09U
#define FS65_M_WU_SOURCE_DEFAULT 0x00U
/**
* Report a wake-up event from CAN or LIN
*/
#define FS65_R_M_PHY_WU_MASK 0x01U
/**
* Report a wake-up event from long duration timer
*/
#define FS65_R_M_LDT_WU_MASK 0x02U
/**
* Report an automatic wake-up event
*/
#define FS65_R_M_AUTO_WU_MASK 0x04U
/**
* Report a wake-up event from IO_0
*/
#define FS65_R_M_IO_0_WU_MASK 0x08U
/**
* Report a wake-up event from IO_2
*/
#define FS65_R_M_IO_2_WU_MASK 0x10U
/**
* Report a wake-up event from IO_3
*/
#define FS65_R_M_IO_3_WU_MASK 0x20U
/**
* Report a wake-up event from IO_4
*/
#define FS65_R_M_IO_4_WU_MASK 0x40U
/**
* Report a wake-up event from IO_5
*/
#define FS65_R_M_IO_5_WU_MASK 0x80U
/**
* Report a wake-up event from CAN or LIN
*/
#define FS65_R_M_PHY_WU_SHIFT 0x00U
/**
* Report a wake-up event from long duration timer
*/
#define FS65_R_M_LDT_WU_SHIFT 0x01U
/**
* Report an automatic wake-up event
*/
#define FS65_R_M_AUTO_WU_SHIFT 0x02U
/**
* Report a wake-up event from IO_0
*/
#define FS65_R_M_IO_0_WU_SHIFT 0x03U
/**
* Report a wake-up event from IO_2
*/
#define FS65_R_M_IO_2_WU_SHIFT 0x04U
/**
* Report a wake-up event from IO_3
*/
#define FS65_R_M_IO_3_WU_SHIFT 0x05U
/**
* Report a wake-up event from IO_4
*/
#define FS65_R_M_IO_4_WU_SHIFT 0x06U
/**
* Report a wake-up event from IO_5
*/
#define FS65_R_M_IO_5_WU_SHIFT 0x07U
/**
* No wake-up
*/
#define FS65_R_M_PHY_WU_NO_EVENT (0x00U << FS65_R_M_PHY_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_PHY_WU_EVENT (0x01U << FS65_R_M_PHY_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_LDT_WU_NO_EVENT (0x00U << FS65_R_M_LDT_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_LDT_WU_EVENT (0x01U << FS65_R_M_LDT_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_AUTO_WU_NO_EVENT (0x00U << FS65_R_M_AUTO_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_AUTO_WU_EVENT (0x01U << FS65_R_M_AUTO_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_IO_0_WU_NO_EVENT (0x00U << FS65_R_M_IO_0_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_IO_0_WU_EVENT (0x01U << FS65_R_M_IO_0_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_IO_2_WU_NO_EVENT (0x00U << FS65_R_M_IO_2_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_IO_2_WU_EVENT (0x01U << FS65_R_M_IO_2_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_IO_3_WU_NO_EVENT (0x00U << FS65_R_M_IO_3_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_IO_3_WU_EVENT (0x01U << FS65_R_M_IO_3_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_IO_4_WU_NO_EVENT (0x00U << FS65_R_M_IO_4_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_IO_4_WU_EVENT (0x01U << FS65_R_M_IO_4_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_IO_5_WU_NO_EVENT (0x00U << FS65_R_M_IO_5_WU_SHIFT)
/**
* Wake-up event detected
*/
#define FS65_R_M_IO_5_WU_EVENT (0x01U << FS65_R_M_IO_5_WU_SHIFT)
/******************************************************************************/
/* DEVICE_ID - Type: R */
/******************************************************************************/
#define FS65_M_DEVICE_ID_ADDR 0x0AU
#define FS65_M_DEVICE_ID_DEFAULT 0x00U
/**
* Device silicon revision
*/
#define FS65_R_M_DEV_REV_MASK 0x07U
/**
* VKAM supply
*/
#define FS65_R_M_VKAM_MASK 0x08U
/**
* CAN or LIN physical layer
*/
#define FS65_R_M_PHY_MASK 0x30U
/**
* VCORE current capability
*/
#define FS65_R_M_VCORE_MASK 0xC0U
/**
* Device silicon revision
*/
#define FS65_R_M_DEV_REV_SHIFT 0x00U
/**
* VKAM supply
*/
#define FS65_R_M_VKAM_SHIFT 0x03U
/**
* CAN or LIN physical layer
*/
#define FS65_R_M_PHY_SHIFT 0x04U
/**
* VCORE current capability
*/
#define FS65_R_M_VCORE_SHIFT 0x06U
/**
* Silicon Rev. 000
*/
#define FS65_R_M_DEV_REV_REV_000 (0x00U << FS65_R_M_DEV_REV_SHIFT)
/**
* Silicon Rev. 001
*/
#define FS65_R_M_DEV_REV_REV_001 (0x01U << FS65_R_M_DEV_REV_SHIFT)
/**
* Silicon Rev. 010
*/
#define FS65_R_M_DEV_REV_REV_010 (0x02U << FS65_R_M_DEV_REV_SHIFT)
/**
* Silicon Rev. 011
*/
#define FS65_R_M_DEV_REV_REV_011 (0x03U << FS65_R_M_DEV_REV_SHIFT)
/**
* Silicon Rev. 100
*/
#define FS65_R_M_DEV_REV_REV_100 (0x04U << FS65_R_M_DEV_REV_SHIFT)
/**
* Silicon Rev. 101
*/
#define FS65_R_M_DEV_REV_REV_101 (0x05U << FS65_R_M_DEV_REV_SHIFT)
/**
* Silicon Rev. 110
*/
#define FS65_R_M_DEV_REV_REV_110 (0x06U << FS65_R_M_DEV_REV_SHIFT)
/**
* Silicon Rev. 111
*/
#define FS65_R_M_DEV_REV_REV_111 (0x07U << FS65_R_M_DEV_REV_SHIFT)
/**
* VKAM off by default
*/
#define FS65_R_M_VKAM_OFF (0x00U << FS65_R_M_VKAM_SHIFT)
/**
* VKAM on by default
*/
#define FS65_R_M_VKAM_ON (0x01U << FS65_R_M_VKAM_SHIFT)
/**
* No CAN/no LIN
*/
#define FS65_R_M_PHY_NOCAN_NOLIN (0x00U << FS65_R_M_PHY_SHIFT)
/**
* CAN only
*/
#define FS65_R_M_PHY_CAN (0x01U << FS65_R_M_PHY_SHIFT)
/**
* LIN only
*/
#define FS65_R_M_PHY_LIN (0x02U << FS65_R_M_PHY_SHIFT)
/**
* CAN and LIN
*/
#define FS65_R_M_PHY_CAN_LIN (0x03U << FS65_R_M_PHY_SHIFT)
/**
* 1.5 A
*/
#define FS65_R_M_VCORE_1_5A (0x00U << FS65_R_M_VCORE_SHIFT)
/**
* 0.8 A
*/
#define FS65_R_M_VCORE_0_8A (0x01U << FS65_R_M_VCORE_SHIFT)
/**
* 0.5 A
*/
#define FS65_R_M_VCORE_0_5A (0x02U << FS65_R_M_VCORE_SHIFT)
/**
* 2.2 A
*/
#define FS65_R_M_VCORE_2_2A (0x03U << FS65_R_M_VCORE_SHIFT)
/******************************************************************************/
/* IO_INPUT - Type: R */
/******************************************************************************/
#define FS65_M_IO_INPUT_ADDR 0x0BU
#define FS65_M_IO_INPUT_DEFAULT 0x00U
/**
* Report IO_0 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_0_MASK 0x01U
/**
* Report IO_2 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_2_MASK 0x08U
/**
* Report IO_3 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_3_MASK 0x10U
/**
* Report IO_4 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_4_MASK 0x40U
/**
* Report IO_5 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_5_MASK 0x80U
/**
* Report IO_0 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_0_SHIFT 0x00U
/**
* Report IO_2 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_2_SHIFT 0x03U
/**
* Report IO_3 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_3_SHIFT 0x04U
/**
* Report IO_4 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_4_SHIFT 0x06U
/**
* Report IO_5 digital state in normal mode. No update in LPOFF mode since wake-up features available
*/
#define FS65_R_M_IO_5_SHIFT 0x07U
/**
* Low
*/
#define FS65_R_M_IO_0_LOW (0x00U << FS65_R_M_IO_0_SHIFT)
/**
* High
*/
#define FS65_R_M_IO_0_HIGH (0x01U << FS65_R_M_IO_0_SHIFT)
/**
* Low
*/
#define FS65_R_M_IO_2_LOW (0x00U << FS65_R_M_IO_2_SHIFT)
/**
* High
*/
#define FS65_R_M_IO_2_HIGH (0x01U << FS65_R_M_IO_2_SHIFT)
/**
* Low
*/
#define FS65_R_M_IO_3_LOW (0x00U << FS65_R_M_IO_3_SHIFT)
/**
* High
*/
#define FS65_R_M_IO_3_HIGH (0x01U << FS65_R_M_IO_3_SHIFT)
/**
* Low
*/
#define FS65_R_M_IO_4_LOW (0x00U << FS65_R_M_IO_4_SHIFT)
/**
* High
*/
#define FS65_R_M_IO_4_HIGH (0x01U << FS65_R_M_IO_4_SHIFT)
/**
* Low
*/
#define FS65_R_M_IO_5_LOW (0x00U << FS65_R_M_IO_5_SHIFT)
/**
* High
*/
#define FS65_R_M_IO_5_HIGH (0x01U << FS65_R_M_IO_5_SHIFT)
/******************************************************************************/
/* DIAG_VPRE - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_VPRE_ADDR 0x0CU
#define FS65_M_DIAG_VPRE_DEFAULT 0x44U
/**
* Report a current limitation condition on VPRE
*/
#define FS65_R_M_ILIM_PRE_MASK 0x02U
/**
* VPRE undervoltage detection
*/
#define FS65_R_M_VPRE_UV_MASK 0x04U
/**
* VPRE overvoltage detection
*/
#define FS65_R_M_VPRE_OV_MASK 0x08U
/**
* Thermal shutdown of VPRE
*/
#define FS65_R_M_TSD_PRE_MASK 0x10U
/**
* Report a thermal warning from VPRE
*/
#define FS65_R_M_TWARN_PRE_MASK 0x20U
/**
* Report the activation state of VPRE SMPS
*/
#define FS65_R_M_VPRE_STATE_MASK 0x40U
/**
* Report a running mode of VPRE
*/
#define FS65_R_M_BOB_MASK 0x80U
/**
* Report a current limitation condition on VPRE
*/
#define FS65_R_M_ILIM_PRE_SHIFT 0x01U
/**
* VPRE undervoltage detection
*/
#define FS65_R_M_VPRE_UV_SHIFT 0x02U
/**
* VPRE overvoltage detection
*/
#define FS65_R_M_VPRE_OV_SHIFT 0x03U
/**
* Thermal shutdown of VPRE
*/
#define FS65_R_M_TSD_PRE_SHIFT 0x04U
/**
* Report a thermal warning from VPRE
*/
#define FS65_R_M_TWARN_PRE_SHIFT 0x05U
/**
* Report the activation state of VPRE SMPS
*/
#define FS65_R_M_VPRE_STATE_SHIFT 0x06U
/**
* Report a running mode of VPRE
*/
#define FS65_R_M_BOB_SHIFT 0x07U
/**
* No current limitation (IPRE_PK < IPRE_LIM)
*/
#define FS65_R_M_ILIM_PRE_NO_LIMITATION (0x00U << FS65_R_M_ILIM_PRE_SHIFT)
/**
* Current limitation (IPRE_PK > IPRE_LIM)
*/
#define FS65_R_M_ILIM_PRE_LIMITATION (0x01U << FS65_R_M_ILIM_PRE_SHIFT)
/**
* No undervoltage (VPRE > VPRE_UV)
*/
#define FS65_R_M_VPRE_UV_NO_UNDERVOLTAGE (0x00U << FS65_R_M_VPRE_UV_SHIFT)
/**
* Undervoltage detected (VPRE < VPRE_UV)
*/
#define FS65_R_M_VPRE_UV_UNDERVOLTAGE (0x01U << FS65_R_M_VPRE_UV_SHIFT)
/**
* No overvoltage (VPRE < VPRE_OV)
*/
#define FS65_R_M_VPRE_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_VPRE_OV_SHIFT)
/**
* Overvoltage detected (VPRE > VPRE_OV)
*/
#define FS65_R_M_VPRE_OV_OVERVOLTAGE (0x01U << FS65_R_M_VPRE_OV_SHIFT)
/**
* No TSD (TJ < TSD_PRE)
*/
#define FS65_R_M_TSD_PRE_NO_TSD (0x00U << FS65_R_M_TSD_PRE_SHIFT)
/**
* TSD occurred (TJ > TSD_PRE)
*/
#define FS65_R_M_TSD_PRE_TSD_OCCURRED (0x01U << FS65_R_M_TSD_PRE_SHIFT)
/**
* No thermal warning (TJ < TWARN_PRE)
*/
#define FS65_R_M_TWARN_PRE_NO_WARNING (0x00U << FS65_R_M_TWARN_PRE_SHIFT)
/**
* Thermal warning (TJ > TWARN_PRE)
*/
#define FS65_R_M_TWARN_PRE_WARNING (0x01U << FS65_R_M_TWARN_PRE_SHIFT)
/**
* SMPS off
*/
#define FS65_R_M_VPRE_STATE_OFF (0x00U << FS65_R_M_VPRE_STATE_SHIFT)
/**
* SMPS on
*/
#define FS65_R_M_VPRE_STATE_ON (0x01U << FS65_R_M_VPRE_STATE_SHIFT)
/**
* Buck
*/
#define FS65_R_M_BOB_BUCK (0x00U << FS65_R_M_BOB_SHIFT)
/**
* Boost
*/
#define FS65_R_M_BOB_BOOST (0x01U << FS65_R_M_BOB_SHIFT)
/******************************************************************************/
/* DIAG_VCORE - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_VCORE_ADDR 0x0DU
#define FS65_M_DIAG_VCORE_DEFAULT 0x44U
/**
* VCORE undervoltage detection
*/
#define FS65_R_M_VCORE_FB_UV_MASK 0x04U
/**
* VCORE overvoltage detection
*/
#define FS65_R_M_VCORE_FB_OV_MASK 0x08U
/**
* Thermal shutdown of VCORE
*/
#define FS65_R_M_TSD_CORE_MASK 0x10U
/**
* Report a thermal warning from VCORE
*/
#define FS65_R_M_TWARN_CORE_MASK 0x20U
/**
* Report the activation state of VCORE SMPS
*/
#define FS65_R_M_VCORE_STATE_MASK 0x40U
/**
* VCORE undervoltage detection
*/
#define FS65_R_M_VCORE_FB_UV_SHIFT 0x02U
/**
* VCORE overvoltage detection
*/
#define FS65_R_M_VCORE_FB_OV_SHIFT 0x03U
/**
* Thermal shutdown of VCORE
*/
#define FS65_R_M_TSD_CORE_SHIFT 0x04U
/**
* Report a thermal warning from VCORE
*/
#define FS65_R_M_TWARN_CORE_SHIFT 0x05U
/**
* Report the activation state of VCORE SMPS
*/
#define FS65_R_M_VCORE_STATE_SHIFT 0x06U
/**
* No undervoltage (VCORE_FB > VCORE_FB_UV)
*/
#define FS65_R_M_VCORE_FB_UV_NO_UNDERVOLTAGE (0x00U << FS65_R_M_VCORE_FB_UV_SHIFT)
/**
* Undervoltage (VCORE_FB < VCORE_FB_UV)
*/
#define FS65_R_M_VCORE_FB_UV_UNDERVOLTAGE (0x01U << FS65_R_M_VCORE_FB_UV_SHIFT)
/**
* No overvoltage (VCORE_FB < VCORE_FB_OV)
*/
#define FS65_R_M_VCORE_FB_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_VCORE_FB_OV_SHIFT)
/**
* Overvoltage detected (VPRE > VPRE_OV)
*/
#define FS65_R_M_VCORE_FB_OV_OVERVOLTAGE (0x01U << FS65_R_M_VCORE_FB_OV_SHIFT)
/**
* No TSD (TJ < TSD_PRE)
*/
#define FS65_R_M_TSD_CORE_NO_TSD (0x00U << FS65_R_M_TSD_CORE_SHIFT)
/**
* TSD occurred (TJ > TSD_CORE)
*/
#define FS65_R_M_TSD_CORE_TSD_OCCURRED (0x01U << FS65_R_M_TSD_CORE_SHIFT)
/**
* No thermal warning (TJ < TWARN_CORE)
*/
#define FS65_R_M_TWARN_CORE_NO_WARNING (0x00U << FS65_R_M_TWARN_CORE_SHIFT)
/**
* Thermal warning (TJ > TWARN_CORE)
*/
#define FS65_R_M_TWARN_CORE_WARNING (0x01U << FS65_R_M_TWARN_CORE_SHIFT)
/**
* SMPS off
*/
#define FS65_R_M_VCORE_STATE_OFF (0x00U << FS65_R_M_VCORE_STATE_SHIFT)
/**
* SMPS on
*/
#define FS65_R_M_VCORE_STATE_ON (0x01U << FS65_R_M_VCORE_STATE_SHIFT)
/******************************************************************************/
/* DIAG_VCCA - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_VCCA_ADDR 0x0EU
#define FS65_M_DIAG_VCCA_DEFAULT 0x04U
/**
* Maximum current limitation duration. Available only when an external PNP is connected
*/
#define FS65_R_M_ILIM_CCA_OFF_MASK 0x01U
/**
* Report a current limitation condition on VCCA
*/
#define FS65_R_M_ILIM_CCA_MASK 0x02U
/**
* VCCA undervoltage detection
*/
#define FS65_R_M_VCCA_UV_MASK 0x04U
/**
* VCCA overvoltage detection
*/
#define FS65_R_M_VCCA_OV_MASK 0x08U
/**
* Thermal shutdown of VCCA
*/
#define FS65_R_M_TSD_CCA_MASK 0x10U
/**
* Report a thermal warning from VCCA. Available only for internal pass MOSFET
*/
#define FS65_R_M_TWARN_CCA_MASK 0x20U
/**
* Maximum current limitation duration. Available only when an external PNP is connected
*/
#define FS65_R_M_ILIM_CCA_OFF_SHIFT 0x00U
/**
* Report a current limitation condition on VCCA
*/
#define FS65_R_M_ILIM_CCA_SHIFT 0x01U
/**
* VCCA undervoltage detection
*/
#define FS65_R_M_VCCA_UV_SHIFT 0x02U
/**
* VCCA overvoltage detection
*/
#define FS65_R_M_VCCA_OV_SHIFT 0x03U
/**
* Thermal shutdown of VCCA
*/
#define FS65_R_M_TSD_CCA_SHIFT 0x04U
/**
* Report a thermal warning from VCCA. Available only for internal pass MOSFET
*/
#define FS65_R_M_TWARN_CCA_SHIFT 0x05U
/**
* T_LIMITATION < TCCA_LIM_OFF
*/
#define FS65_R_M_ILIM_CCA_OFF_NO_LIMITATION (0x00U << FS65_R_M_ILIM_CCA_OFF_SHIFT)
/**
* T_LIMITATION > TCCA_LIM_OFF
*/
#define FS65_R_M_ILIM_CCA_OFF_LIMITATION (0x01U << FS65_R_M_ILIM_CCA_OFF_SHIFT)
/**
* No current limitation (ICCA < ICCA_LIM)
*/
#define FS65_R_M_ILIM_CCA_NO_LIMITATION (0x00U << FS65_R_M_ILIM_CCA_SHIFT)
/**
* Current limitation (ICCA > ICCA_LIM)
*/
#define FS65_R_M_ILIM_CCA_LIMITATION (0x01U << FS65_R_M_ILIM_CCA_SHIFT)
/**
* No undervoltage (VCCA > VCCA_UV)
*/
#define FS65_R_M_VCCA_UV_NO_UNDERVOLTAGE (0x00U << FS65_R_M_VCCA_UV_SHIFT)
/**
* Undervoltage detected (VCCA < VCCA_UV)
*/
#define FS65_R_M_VCCA_UV_UNDERVOLTAGE (0x01U << FS65_R_M_VCCA_UV_SHIFT)
/**
* No overvoltage (VCCA < VCCA_OV)
*/
#define FS65_R_M_VCCA_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_VCCA_OV_SHIFT)
/**
* Overvoltage detected (VCCA > VCCA_OV)
*/
#define FS65_R_M_VCCA_OV_OVERVOLTAGE (0x01U << FS65_R_M_VCCA_OV_SHIFT)
/**
* NO TSD (TJ < TSD_CCA)
*/
#define FS65_R_M_TSD_CCA_NO_TSD (0x00U << FS65_R_M_TSD_CCA_SHIFT)
/**
* TSD occurred (TJ > TSD_CCA)
*/
#define FS65_R_M_TSD_CCA_TSD_OCCURRED (0x01U << FS65_R_M_TSD_CCA_SHIFT)
/**
* No thermal warning (TJ < TWARN_CCA)
*/
#define FS65_R_M_TWARN_CCA_NO_WARNING (0x00U << FS65_R_M_TWARN_CCA_SHIFT)
/**
* Thermal warning (TJ > TWARN_CCA)
*/
#define FS65_R_M_TWARN_CCA_WARNING (0x01U << FS65_R_M_TWARN_CCA_SHIFT)
/******************************************************************************/
/* DIAG_VAUX - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_VAUX_ADDR 0x0FU
#define FS65_M_DIAG_VAUX_DEFAULT 0x04U
/**
* Maximum current limitation duration
*/
#define FS65_R_M_ILIM_AUX_OFF_MASK 0x01U
/**
* Report a current limitation condition on VAUX
*/
#define FS65_R_M_ILIM_AUX_MASK 0x02U
/**
* VAUX undervoltage detection
*/
#define FS65_R_M_VAUX_UV_MASK 0x04U
/**
* VAUX overvoltage detection
*/
#define FS65_R_M_VAUX_OV_MASK 0x08U
/**
* Thermal shutdown of VAUX
*/
#define FS65_R_M_TSD_AUX_MASK 0x10U
/**
* Maximum current limitation duration
*/
#define FS65_R_M_ILIM_AUX_OFF_SHIFT 0x00U
/**
* Report a current limitation condition on VAUX
*/
#define FS65_R_M_ILIM_AUX_SHIFT 0x01U
/**
* VAUX undervoltage detection
*/
#define FS65_R_M_VAUX_UV_SHIFT 0x02U
/**
* VAUX overvoltage detection
*/
#define FS65_R_M_VAUX_OV_SHIFT 0x03U
/**
* Thermal shutdown of VAUX
*/
#define FS65_R_M_TSD_AUX_SHIFT 0x04U
/**
* T_LIMITATION < TAUX_LIM_OFF
*/
#define FS65_R_M_ILIM_AUX_OFF_NO_LIMITATION (0x00U << FS65_R_M_ILIM_AUX_OFF_SHIFT)
/**
* T_LIMITATION > TAUX_LIM_OFF
*/
#define FS65_R_M_ILIM_AUX_OFF_LIMITATION (0x01U << FS65_R_M_ILIM_AUX_OFF_SHIFT)
/**
* No current limitation (IAUX < IAUX_LIM)
*/
#define FS65_R_M_ILIM_AUX_NO_LIMITATION (0x00U << FS65_R_M_ILIM_AUX_SHIFT)
/**
* Current limitation (IAUX > IAUX_LIM)
*/
#define FS65_R_M_ILIM_AUX_LIMITATION (0x01U << FS65_R_M_ILIM_AUX_SHIFT)
/**
* No undervoltage (VAUX > VAUX_UV)
*/
#define FS65_R_M_VAUX_UV_NO_UNDERVOLTAGE (0x00U << FS65_R_M_VAUX_UV_SHIFT)
/**
* Undervoltage detected (VAUX < VAUX_UV)
*/
#define FS65_R_M_VAUX_UV_UNDERVOLTAGE (0x01U << FS65_R_M_VAUX_UV_SHIFT)
/**
* No overvoltage (VAUX < VAUX_OV)
*/
#define FS65_R_M_VAUX_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_VAUX_OV_SHIFT)
/**
* Overvoltage detected (VAUX > VAUX_OV)
*/
#define FS65_R_M_VAUX_OV_OVERVOLTAGE (0x01U << FS65_R_M_VAUX_OV_SHIFT)
/**
* No TSD (TJ < TSD_AUX)
*/
#define FS65_R_M_TSD_AUX_NO_TSD (0x00U << FS65_R_M_TSD_AUX_SHIFT)
/**
* TSD occurred (TJ > TSD_AUX)
*/
#define FS65_R_M_TSD_AUX_TSD_OCCURRED (0x01U << FS65_R_M_TSD_AUX_SHIFT)
/******************************************************************************/
/* DIAG_VSUP_VCAN - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_VSUP_VCAN_ADDR 0x10U
#define FS65_M_DIAG_VSUP_VCAN_DEFAULT 0xC4U
/**
* Report a current limitation condition on VCAN
*/
#define FS65_R_M_ILIM_CAN_MASK 0x02U
/**
* VCAN undervoltage detection
*/
#define FS65_R_M_VCAN_UV_MASK 0x04U
/**
* VCAN overvoltage detection
*/
#define FS65_R_M_VCAN_OV_MASK 0x08U
/**
* Thermal shutdown of VCAN
*/
#define FS65_R_M_TSD_CAN_MASK 0x10U
/**
* Input power feed forward (IPFF)
*/
#define FS65_R_M_IPFF_MASK 0x20U
/**
* Detection of VSUP below VSUP_UV_7
*/
#define FS65_R_M_VSUP_UV_7_MASK 0x40U
/**
* Detection of battery voltage below VSNS_UV
*/
#define FS65_R_M_VSNS_UV_MASK 0x80U
/**
* Report a current limitation condition on VCAN
*/
#define FS65_R_M_ILIM_CAN_SHIFT 0x01U
/**
* VCAN undervoltage detection
*/
#define FS65_R_M_VCAN_UV_SHIFT 0x02U
/**
* VCAN overvoltage detection
*/
#define FS65_R_M_VCAN_OV_SHIFT 0x03U
/**
* Thermal shutdown of VCAN
*/
#define FS65_R_M_TSD_CAN_SHIFT 0x04U
/**
* Input power feed forward (IPFF)
*/
#define FS65_R_M_IPFF_SHIFT 0x05U
/**
* Detection of VSUP below VSUP_UV_7
*/
#define FS65_R_M_VSUP_UV_7_SHIFT 0x06U
/**
* Detection of battery voltage below VSNS_UV
*/
#define FS65_R_M_VSNS_UV_SHIFT 0x07U
/**
* No current limitation (ICAN < ICAN_LIM)
*/
#define FS65_R_M_ILIM_CAN_NO_LIMITATION (0x00U << FS65_R_M_ILIM_CAN_SHIFT)
/**
* Current limitation (ICAN > ICAN _LIM)
*/
#define FS65_R_M_ILIM_CAN_LIMITATION (0x01U << FS65_R_M_ILIM_CAN_SHIFT)
/**
* No undervoltage (VCAN > VCAN_UV)
*/
#define FS65_R_M_VCAN_UV_NO_UNDERVOLTAGE (0x00U << FS65_R_M_VCAN_UV_SHIFT)
/**
* Undervoltage detected (VCAN < VCAN_UV)
*/
#define FS65_R_M_VCAN_UV_UNDERVOLTAGE (0x01U << FS65_R_M_VCAN_UV_SHIFT)
/**
* No overvoltage (VCAN < VCAN_OV)
*/
#define FS65_R_M_VCAN_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_VCAN_OV_SHIFT)
/**
* Overvoltage detected (VCAN > VCAN_OV)
*/
#define FS65_R_M_VCAN_OV_OVERVOLTAGE (0x01U << FS65_R_M_VCAN_OV_SHIFT)
/**
* NO TSD (TJ < TSD_CAN)
*/
#define FS65_R_M_TSD_CAN_NO_TSD (0x00U << FS65_R_M_TSD_CAN_SHIFT)
/**
* TSD occurred (TJ > TSD_CAN)
*/
#define FS65_R_M_TSD_CAN_TSD_OCCURRED (0x01U << FS65_R_M_TSD_CAN_SHIFT)
/**
* Normal operation
*/
#define FS65_R_M_IPFF_NORMAL (0x00U << FS65_R_M_IPFF_SHIFT)
/**
* IPFF mode activated
*/
#define FS65_R_M_IPFF_IPFF (0x01U << FS65_R_M_IPFF_SHIFT)
/**
* VSUP > VSUP_UV_7
*/
#define FS65_R_M_VSUP_UV_7_VSUP_G (0x00U << FS65_R_M_VSUP_UV_7_SHIFT)
/**
* VSUP < VSUP_UV_7
*/
#define FS65_R_M_VSUP_UV_7_VSUP_L (0x01U << FS65_R_M_VSUP_UV_7_SHIFT)
/**
* VBAT > VSNS_UV
*/
#define FS65_R_M_VSNS_UV_VBAT_G (0x00U << FS65_R_M_VSNS_UV_SHIFT)
/**
* VBAT < VSNS_UV
*/
#define FS65_R_M_VSNS_UV_VBAT_L (0x01U << FS65_R_M_VSNS_UV_SHIFT)
/******************************************************************************/
/* DIAG_CAN_FD - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_CAN_FD_ADDR 0x11U
#define FS65_M_DIAG_CAN_FD_DEFAULT 0x00U
/**
* TXD dominant clamping detection (short-circuit to GND)
*/
#define FS65_R_M_TXD_DOM_MASK 0x01U
/**
* RXD recessive clamping detection (short-circuit to 5.0 V)
*/
#define FS65_R_M_RXD_REC_MASK 0x02U
/**
* CAN Bus dominant clamping detection
*/
#define FS65_R_M_CAN_DOM_MASK 0x08U
/**
* CANL short-circuit to GND detection
*/
#define FS65_R_M_CANL_GND_MASK 0x10U
/**
* CANL short-circuit to battery detection
*/
#define FS65_R_M_CANL_BATT_MASK 0x20U
/**
* CANH short-circuit to GND detection
*/
#define FS65_R_M_CANH_GND_MASK 0x40U
/**
* CANH short-circuit to battery detection
*/
#define FS65_R_M_CANH_BATT_MASK 0x80U
/**
* TXD dominant clamping detection (short-circuit to GND)
*/
#define FS65_R_M_TXD_DOM_SHIFT 0x00U
/**
* RXD recessive clamping detection (short-circuit to 5.0 V)
*/
#define FS65_R_M_RXD_REC_SHIFT 0x01U
/**
* CAN Bus dominant clamping detection
*/
#define FS65_R_M_CAN_DOM_SHIFT 0x03U
/**
* CANL short-circuit to GND detection
*/
#define FS65_R_M_CANL_GND_SHIFT 0x04U
/**
* CANL short-circuit to battery detection
*/
#define FS65_R_M_CANL_BATT_SHIFT 0x05U
/**
* CANH short-circuit to GND detection
*/
#define FS65_R_M_CANH_GND_SHIFT 0x06U
/**
* CANH short-circuit to battery detection
*/
#define FS65_R_M_CANH_BATT_SHIFT 0x07U
/**
* No failure
*/
#define FS65_R_M_TXD_DOM_NO_FAILURE (0x00U << FS65_R_M_TXD_DOM_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_TXD_DOM_FAILURE (0x01U << FS65_R_M_TXD_DOM_SHIFT)
/**
* No failure
*/
#define FS65_R_M_RXD_REC_NO_FAILURE (0x00U << FS65_R_M_RXD_REC_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_RXD_REC_FAILURE (0x01U << FS65_R_M_RXD_REC_SHIFT)
/**
* No failure
*/
#define FS65_R_M_CAN_DOM_NO_FAILURE (0x00U << FS65_R_M_CAN_DOM_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_CAN_DOM_FAILURE (0x01U << FS65_R_M_CAN_DOM_SHIFT)
/**
* No failure
*/
#define FS65_R_M_CANL_GND_NO_FAILURE (0x00U << FS65_R_M_CANL_GND_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_CANL_GND_FAILURE (0x01U << FS65_R_M_CANL_GND_SHIFT)
/**
* No failure
*/
#define FS65_R_M_CANL_BATT_NO_FAILURE (0x00U << FS65_R_M_CANL_BATT_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_CANL_BATT_FAILURE (0x01U << FS65_R_M_CANL_BATT_SHIFT)
/**
* No failure
*/
#define FS65_R_M_CANH_GND_NO_FAILURE (0x00U << FS65_R_M_CANH_GND_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_CANH_GND_FAILURE (0x01U << FS65_R_M_CANH_GND_SHIFT)
/**
* No failure
*/
#define FS65_R_M_CANH_BATT_NO_FAILURE (0x00U << FS65_R_M_CANH_BATT_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_CANH_BATT_FAILURE (0x01U << FS65_R_M_CANH_BATT_SHIFT)
/******************************************************************************/
/* DIAG_CAN_LIN - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_CAN_LIN_ADDR 0x12U
#define FS65_M_DIAG_CAN_LIN_DEFAULT 0x00U
/**
* CAN overcurrent detection
*/
#define FS65_R_M_CAN_OC_MASK 0x01U
/**
* CAN overtemperature detection
*/
#define FS65_R_M_CAN_OT_MASK 0x02U
/**
* LIN overtemperature detection
*/
#define FS65_R_M_LIN_OT_MASK 0x08U
/**
* LIN RXD recessive clamping detection (short-circuit to 5.0 V)
*/
#define FS65_R_M_RXDL_REC_MASK 0x10U
/**
* LIN TXD dominant clamping detection (short-circuit to GND)
*/
#define FS65_R_M_TDXL_DOM_MASK 0x40U
/**
* LIN bus dominant clamping detection
*/
#define FS65_R_M_LIN_DOM_MASK 0x80U
/**
* CAN overcurrent detection
*/
#define FS65_R_M_CAN_OC_SHIFT 0x00U
/**
* CAN overtemperature detection
*/
#define FS65_R_M_CAN_OT_SHIFT 0x01U
/**
* LIN overtemperature detection
*/
#define FS65_R_M_LIN_OT_SHIFT 0x03U
/**
* LIN RXD recessive clamping detection (short-circuit to 5.0 V)
*/
#define FS65_R_M_RXDL_REC_SHIFT 0x04U
/**
* LIN TXD dominant clamping detection (short-circuit to GND)
*/
#define FS65_R_M_TDXL_DOM_SHIFT 0x06U
/**
* LIN bus dominant clamping detection
*/
#define FS65_R_M_LIN_DOM_SHIFT 0x07U
/**
* No failure
*/
#define FS65_R_M_CAN_OC_NO_FAILURE (0x00U << FS65_R_M_CAN_OC_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_CAN_OC_FAILURE (0x01U << FS65_R_M_CAN_OC_SHIFT)
/**
* No failure
*/
#define FS65_R_M_CAN_OT_NO_FAILURE (0x00U << FS65_R_M_CAN_OT_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_CAN_OT_FAILURE (0x01U << FS65_R_M_CAN_OT_SHIFT)
/**
* No failure
*/
#define FS65_R_M_LIN_OT_NO_FAILURE (0x00U << FS65_R_M_LIN_OT_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_LIN_OT_FAILURE (0x01U << FS65_R_M_LIN_OT_SHIFT)
/**
* No failure
*/
#define FS65_R_M_RXDL_REC_NO_FAILURE (0x00U << FS65_R_M_RXDL_REC_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_RXDL_REC_FAILURE (0x01U << FS65_R_M_RXDL_REC_SHIFT)
/**
* No failure
*/
#define FS65_R_M_TDXL_DOM_NO_FAILURE (0x00U << FS65_R_M_TDXL_DOM_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_TDXL_DOM_FAILURE (0x01U << FS65_R_M_TDXL_DOM_SHIFT)
/**
* No failure
*/
#define FS65_R_M_LIN_DOM_NO_FAILURE (0x00U << FS65_R_M_LIN_DOM_SHIFT)
/**
* Failure detected
*/
#define FS65_R_M_LIN_DOM_FAILURE (0x01U << FS65_R_M_LIN_DOM_SHIFT)
/******************************************************************************/
/* DIAG_SPI - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_SPI_ADDR 0x13U
#define FS65_M_DIAG_SPI_DEFAULT 0x00U
/**
* SPI parity bit error detection
*/
#define FS65_R_M_SPI_PARITY_MASK 0x02U
/**
* Invalid SPI access (wrong write or read, write to INIT registers in normal mode, wrong address)
*/
#define FS65_R_M_SPI_REQ_MASK 0x08U
/**
* SCLK error detection
*/
#define FS65_R_M_SPI_CLK_MASK 0x20U
/**
* Secured SPI communication check
*/
#define FS65_R_M_SPI_ERR_MASK 0x80U
/**
* SPI parity bit error detection
*/
#define FS65_R_M_SPI_PARITY_SHIFT 0x01U
/**
* Invalid SPI access (wrong write or read, write to INIT registers in normal mode, wrong address)
*/
#define FS65_R_M_SPI_REQ_SHIFT 0x03U
/**
* SCLK error detection
*/
#define FS65_R_M_SPI_CLK_SHIFT 0x05U
/**
* Secured SPI communication check
*/
#define FS65_R_M_SPI_ERR_SHIFT 0x07U
/**
* Parity bit ok
*/
#define FS65_R_M_SPI_PARITY_OK (0x00U << FS65_R_M_SPI_PARITY_SHIFT)
/**
* Parity bit error
*/
#define FS65_R_M_SPI_PARITY_ERROR (0x01U << FS65_R_M_SPI_PARITY_SHIFT)
/**
* No error
*/
#define FS65_R_M_SPI_REQ_NO_ERROR (0x00U << FS65_R_M_SPI_REQ_SHIFT)
/**
* SPI violation
*/
#define FS65_R_M_SPI_REQ_SPI_VIOLATION (0x01U << FS65_R_M_SPI_REQ_SHIFT)
/**
* 16 clock cycles during NCS low
*/
#define FS65_R_M_SPI_CLK_16_CLK_CYCLES (0x00U << FS65_R_M_SPI_CLK_SHIFT)
/**
* Wrong number of clock cycles (<16 or > 16)
*/
#define FS65_R_M_SPI_CLK_WRONG_NUMBER (0x01U << FS65_R_M_SPI_CLK_SHIFT)
/**
* No error
*/
#define FS65_R_M_SPI_ERR_NO_ERROR (0x00U << FS65_R_M_SPI_ERR_SHIFT)
/**
* Error detected in the secured bits
*/
#define FS65_R_M_SPI_ERR_ERROR (0x01U << FS65_R_M_SPI_ERR_SHIFT)
/******************************************************************************/
/* MODE - Type: RW */
/******************************************************************************/
#define FS65_M_MODE_ADDR 0x15U
#define FS65_M_MODE_DEFAULT 0x08U
/**
* Report if the device resume from LPOFF-sleep or LPOFF_AUTO_WU mode
*/
#define FS65_R_M_LPOFF_MASK 0x01U
/**
* Report if the device resume from deep fail-safe mode
*/
#define FS65_R_M_DFS_MASK 0x02U
/**
* Report if normal mode of the main logic state machine is entered
*/
#define FS65_R_M_NORMAL_MASK 0x04U
/**
* Report if INIT mode of the main logic state machine is entered
*/
#define FS65_R_M_INIT_MASK 0x08U
/**
* Request for an INT pulse
*/
#define FS65_W_M_INT_REQ_MASK 0x10U
/**
* Configure the device in LPOFF-SLEEP
*/
#define FS65_W_M_GO_LPOFF_MASK 0x20U
/**
* Configure the device in LPOFF_AUTO_WU
*/
#define FS65_W_M_LPOFF_AUTO_WU_MASK 0x40U
/**
* VKAM control (default state depends on part number)
*/
#define FS65_RW_M_VKAM_EN_MASK 0x80U
/**
* Report if the device resume from LPOFF-sleep or LPOFF_AUTO_WU mode
*/
#define FS65_R_M_LPOFF_SHIFT 0x00U
/**
* Report if the device resume from deep fail-safe mode
*/
#define FS65_R_M_DFS_SHIFT 0x01U
/**
* Report if normal mode of the main logic state machine is entered
*/
#define FS65_R_M_NORMAL_SHIFT 0x02U
/**
* Report if INIT mode of the main logic state machine is entered
*/
#define FS65_R_M_INIT_SHIFT 0x03U
/**
* Request for an INT pulse
*/
#define FS65_W_M_INT_REQ_SHIFT 0x04U
/**
* Configure the device in LPOFF-SLEEP
*/
#define FS65_W_M_GO_LPOFF_SHIFT 0x05U
/**
* Configure the device in LPOFF_AUTO_WU
*/
#define FS65_W_M_LPOFF_AUTO_WU_SHIFT 0x06U
/**
* VKAM control (default state depends on part number)
*/
#define FS65_RW_M_VKAM_EN_SHIFT 0x07U
/**
* Not in LPOFF
*/
#define FS65_R_M_LPOFF_NOT_LPOFF (0x00U << FS65_R_M_LPOFF_SHIFT)
/**
* Resume from LPOFF
*/
#define FS65_R_M_LPOFF_RESUME_LPOFF (0x01U << FS65_R_M_LPOFF_SHIFT)
/**
* Not in deep fail-safe
*/
#define FS65_R_M_DFS_NOT_DFS (0x00U << FS65_R_M_DFS_SHIFT)
/**
* Resume from deep fail-safe
*/
#define FS65_R_M_DFS_RESUME_DFS (0x01U << FS65_R_M_DFS_SHIFT)
/**
* Not in normal mode
*/
#define FS65_R_M_NORMAL_NOT_NORMAL (0x00U << FS65_R_M_NORMAL_SHIFT)
/**
* Normal mode
*/
#define FS65_R_M_NORMAL_NORMAL (0x01U << FS65_R_M_NORMAL_SHIFT)
/**
* Not in INIT mode
*/
#define FS65_R_M_INIT_NOT_INIT (0x00U << FS65_R_M_INIT_SHIFT)
/**
* INIT mode
*/
#define FS65_R_M_INIT_INIT (0x01U << FS65_R_M_INIT_SHIFT)
/**
* No Request
*/
#define FS65_W_M_INT_REQ_NO (0x00U << FS65_W_M_INT_REQ_SHIFT)
/**
* Request for an INT pulse
*/
#define FS65_W_M_INT_REQ_INT_REQ (0x01U << FS65_W_M_INT_REQ_SHIFT)
/**
* No action
*/
#define FS65_W_M_GO_LPOFF_NO_ACTION (0x00U << FS65_W_M_GO_LPOFF_SHIFT)
/**
* Go to LPOFF mode and wait for wake-up event
*/
#define FS65_W_M_GO_LPOFF_LPOFF (0x01U << FS65_W_M_GO_LPOFF_SHIFT)
/**
* No action
*/
#define FS65_W_M_LPOFF_AUTO_WU_NO_ACTION (0x00U << FS65_W_M_LPOFF_AUTO_WU_SHIFT)
/**
* Go to LPOFF mode and wake-up automatically after 1.0 ms
*/
#define FS65_W_M_LPOFF_AUTO_WU_LPOFF (0x01U << FS65_W_M_LPOFF_AUTO_WU_SHIFT)
/**
* DISABLED
*/
#define FS65_RW_M_VKAM_EN_DISABLED (0x00U << FS65_RW_M_VKAM_EN_SHIFT)
/**
* ENABLED
*/
#define FS65_RW_M_VKAM_EN_ENABLED (0x01U << FS65_RW_M_VKAM_EN_SHIFT)
/******************************************************************************/
/* REG_MODE - Type: RW */
/******************************************************************************/
#define FS65_M_REG_MODE_ADDR 0x16U
#define FS65_M_REG_MODE_DEFAULT 0x0FU
/**
* VCAN control
*/
#define FS65_R_M_VCAN_EN_MASK 0x01U
/**
* VAUX control (switch off not recommended if VAUX is safety critical)
*/
#define FS65_R_M_VAUX_EN_MASK 0x02U
/**
* VCCA control (switch off not recommended if VCCA is safety critical)
*/
#define FS65_R_M_VCCA_EN_MASK 0x04U
/**
* VCORE control (switch off not recommended if VCORE is safety critical)
*/
#define FS65_R_M_VCORE_EN_MASK 0x08U
/**
* VCAN control
*/
#define FS65_W_M_VCAN_EN_MASK 0x10U
/**
* VAUX control (switch off not recommended if VAUX is safety critical)
*/
#define FS65_W_M_VAUX_EN_MASK 0x20U
/**
* VCCA control (switch off not recommended if VCCA is safety critical)
*/
#define FS65_W_M_VCCA_EN_MASK 0x40U
/**
* VCORE control (switch off not recommended if VCORE is safety critical)
*/
#define FS65_W_M_VCORE_EN_MASK 0x80U
/**
* VCAN control
*/
#define FS65_R_M_VCAN_EN_SHIFT 0x00U
/**
* VAUX control (switch off not recommended if VAUX is safety critical)
*/
#define FS65_R_M_VAUX_EN_SHIFT 0x01U
/**
* VCCA control (switch off not recommended if VCCA is safety critical)
*/
#define FS65_R_M_VCCA_EN_SHIFT 0x02U
/**
* VCORE control (switch off not recommended if VCORE is safety critical)
*/
#define FS65_R_M_VCORE_EN_SHIFT 0x03U
/**
* VCAN control
*/
#define FS65_W_M_VCAN_EN_SHIFT 0x04U
/**
* VAUX control (switch off not recommended if VAUX is safety critical)
*/
#define FS65_W_M_VAUX_EN_SHIFT 0x05U
/**
* VCCA control (switch off not recommended if VCCA is safety critical)
*/
#define FS65_W_M_VCCA_EN_SHIFT 0x06U
/**
* VCORE control (switch off not recommended if VCORE is safety critical)
*/
#define FS65_W_M_VCORE_EN_SHIFT 0x07U
/**
* Disabled
*/
#define FS65_R_M_VCAN_EN_DISABLED (0x00U << FS65_R_M_VCAN_EN_SHIFT)
/**
* Enabled
*/
#define FS65_R_M_VCAN_EN_ENABLED (0x01U << FS65_R_M_VCAN_EN_SHIFT)
/**
* Disabled
*/
#define FS65_R_M_VAUX_EN_DISABLED (0x00U << FS65_R_M_VAUX_EN_SHIFT)
/**
* Enabled
*/
#define FS65_R_M_VAUX_EN_ENABLED (0x01U << FS65_R_M_VAUX_EN_SHIFT)
/**
* Disabled
*/
#define FS65_R_M_VCCA_EN_DISABLED (0x00U << FS65_R_M_VCCA_EN_SHIFT)
/**
* Enabled
*/
#define FS65_R_M_VCCA_EN_ENABLED (0x01U << FS65_R_M_VCCA_EN_SHIFT)
/**
* Disabled
*/
#define FS65_R_M_VCORE_EN_DISABLED (0x00U << FS65_R_M_VCORE_EN_SHIFT)
/**
* Enabled
*/
#define FS65_R_M_VCORE_EN_ENABLED (0x01U << FS65_R_M_VCORE_EN_SHIFT)
/**
* Disabled
*/
#define FS65_W_M_VCAN_EN_DISABLED (0x00U << FS65_W_M_VCAN_EN_SHIFT)
/**
* Enabled
*/
#define FS65_W_M_VCAN_EN_ENABLED (0x01U << FS65_W_M_VCAN_EN_SHIFT)
/**
* Disabled
*/
#define FS65_W_M_VAUX_EN_DISABLED (0x00U << FS65_W_M_VAUX_EN_SHIFT)
/**
* Enabled
*/
#define FS65_W_M_VAUX_EN_ENABLED (0x01U << FS65_W_M_VAUX_EN_SHIFT)
/**
* Disabled
*/
#define FS65_W_M_VCCA_EN_DISABLED (0x00U << FS65_W_M_VCCA_EN_SHIFT)
/**
* Enabled
*/
#define FS65_W_M_VCCA_EN_ENABLED (0x01U << FS65_W_M_VCCA_EN_SHIFT)
/**
* Disabled
*/
#define FS65_W_M_VCORE_EN_DISABLED (0x00U << FS65_W_M_VCORE_EN_SHIFT)
/**
* Enabled
*/
#define FS65_W_M_VCORE_EN_ENABLED (0x01U << FS65_W_M_VCORE_EN_SHIFT)
/******************************************************************************/
/* IO_OUT_AMUX - Type: RW */
/******************************************************************************/
#define FS65_M_IO_OUT_AMUX_ADDR 0x17U
#define FS65_M_IO_OUT_AMUX_DEFAULT 0x00U
/**
* Select AMUX output
*/
#define FS65_RW_M_AMUX_MASK 0x07U
/**
* Configure IO_4 output gate driver state
*/
#define FS65_RW_M_IO_OUT_4_MASK 0x40U
/**
* Enable the output gate driver capability for IO_4
*/
#define FS65_RW_M_IO_OUT_4_EN_MASK 0x80U
/**
* Select AMUX output
*/
#define FS65_RW_M_AMUX_SHIFT 0x00U
/**
* Configure IO_4 output gate driver state
*/
#define FS65_RW_M_IO_OUT_4_SHIFT 0x06U
/**
* Enable the output gate driver capability for IO_4
*/
#define FS65_RW_M_IO_OUT_4_EN_SHIFT 0x07U
/**
* VREF
*/
#define FS65_RW_M_AMUX_VREF (0x00U << FS65_RW_M_AMUX_SHIFT)
/**
* VSNS wide range
*/
#define FS65_RW_M_AMUX_VSNS_W (0x01U << FS65_RW_M_AMUX_SHIFT)
/**
* IO_0 wide range
*/
#define FS65_RW_M_AMUX_IO_0_W (0x02U << FS65_RW_M_AMUX_SHIFT)
/**
* IO_5 wide range
*/
#define FS65_RW_M_AMUX_IO_5_W (0x03U << FS65_RW_M_AMUX_SHIFT)
/**
* VSNS tight range
*/
#define FS65_RW_M_AMUX_VSNS_T (0x04U << FS65_RW_M_AMUX_SHIFT)
/**
* IO_0 tight range
*/
#define FS65_RW_M_AMUX_IO_0_T (0x05U << FS65_RW_M_AMUX_SHIFT)
/**
* IO_5 tight range/VKAM
*/
#define FS65_RW_M_AMUX_IO_5_T (0x06U << FS65_RW_M_AMUX_SHIFT)
/**
* Die Temperature Sensor
*/
#define FS65_RW_M_AMUX_TEMP_SENSOR (0x07U << FS65_RW_M_AMUX_SHIFT)
/**
* Low
*/
#define FS65_RW_M_IO_OUT_4_LOW (0x00U << FS65_RW_M_IO_OUT_4_SHIFT)
/**
* High
*/
#define FS65_RW_M_IO_OUT_4_HIGH (0x01U << FS65_RW_M_IO_OUT_4_SHIFT)
/**
* High-impedance (IO_4 configured as input)
*/
#define FS65_RW_M_IO_OUT_4_EN_Z (0x00U << FS65_RW_M_IO_OUT_4_EN_SHIFT)
/**
* Enabled (IO_4 configured as output gate driver)
*/
#define FS65_RW_M_IO_OUT_4_EN_ENABLED (0x01U << FS65_RW_M_IO_OUT_4_EN_SHIFT)
/******************************************************************************/
/* CAN_LIN_MODE - Type: RW */
/******************************************************************************/
#define FS65_M_CAN_LIN_MODE_ADDR 0x18U
#define FS65_M_CAN_LIN_MODE_DEFAULT 0xB4U
/**
* Report a wake-up event from the LIN
*/
#define FS65_R_M_LIN_WU_MASK 0x01U
/**
* Report a wake-up event from the CAN
*/
#define FS65_R_M_CAN_WU_MASK 0x02U
/**
* Automatic LIN mode disable
*/
#define FS65_RW_M_LIN_AUTO_DIS_MASK 0x04U
/**
* Configure the LIN mode
*/
#define FS65_RW_M_LIN_MODE_MASK 0x18U
/**
* Automatic CAN Tx disable
*/
#define FS65_RW_M_CAN_AUTO_DIS_MASK 0x20U
/**
* Configure the CAN mode
*/
#define FS65_RW_M_CAN_MODE_MASK 0xC0U
/**
* Report a wake-up event from the LIN
*/
#define FS65_R_M_LIN_WU_SHIFT 0x00U
/**
* Report a wake-up event from the CAN
*/
#define FS65_R_M_CAN_WU_SHIFT 0x01U
/**
* Automatic LIN mode disable
*/
#define FS65_RW_M_LIN_AUTO_DIS_SHIFT 0x02U
/**
* Configure the LIN mode
*/
#define FS65_RW_M_LIN_MODE_SHIFT 0x03U
/**
* Automatic CAN Tx disable
*/
#define FS65_RW_M_CAN_AUTO_DIS_SHIFT 0x05U
/**
* Configure the CAN mode
*/
#define FS65_RW_M_CAN_MODE_SHIFT 0x06U
/**
* No wake-up
*/
#define FS65_R_M_LIN_WU_NO_WU (0x00U << FS65_R_M_LIN_WU_SHIFT)
/**
* Wake-up detected
*/
#define FS65_R_M_LIN_WU_WU (0x01U << FS65_R_M_LIN_WU_SHIFT)
/**
* No wake-up
*/
#define FS65_R_M_CAN_WU_NO_WU (0x00U << FS65_R_M_CAN_WU_SHIFT)
/**
* Wake-up detected
*/
#define FS65_R_M_CAN_WU_WU (0x01U << FS65_R_M_CAN_WU_SHIFT)
/**
* No auto disable
*/
#define FS65_RW_M_LIN_AUTO_DIS_NO (0x00U << FS65_RW_M_LIN_AUTO_DIS_SHIFT)
/**
* Reset LIN_mode from 11 to 01 on LIN_OT or TXDL_DOM or RXDL_REC event
*/
#define FS65_RW_M_LIN_AUTO_DIS_RESET (0x01U << FS65_RW_M_LIN_AUTO_DIS_SHIFT)
/**
* Sleep/no wake-up capability
*/
#define FS65_RW_M_LIN_MODE_SLN_WU (0x00U << FS65_RW_M_LIN_MODE_SHIFT)
/**
* Listen only
*/
#define FS65_RW_M_LIN_MODE_LISTEN_ONLY (0x01U << FS65_RW_M_LIN_MODE_SHIFT)
/**
* Sleep/wake-up capability
*/
#define FS65_RW_M_LIN_MODE_SL_WU (0x02U << FS65_RW_M_LIN_MODE_SHIFT)
/**
* Normal operation mode
*/
#define FS65_RW_M_LIN_MODE_NORMAL (0x03U << FS65_RW_M_LIN_MODE_SHIFT)
/**
* NO auto disable
*/
#define FS65_RW_M_CAN_AUTO_DIS_NO (0x00U << FS65_RW_M_CAN_AUTO_DIS_SHIFT)
/**
* Reset CAN_mode from 11 to 01 on CAN_OT or TXD_DOM or RXD_REC event
*/
#define FS65_RW_M_CAN_AUTO_DIS_RESET (0x01U << FS65_RW_M_CAN_AUTO_DIS_SHIFT)
/**
* Sleep/no wake-up capability
*/
#define FS65_RW_M_CAN_MODE_SLN_WU (0x00U << FS65_RW_M_CAN_MODE_SHIFT)
/**
* Listen only
*/
#define FS65_RW_M_CAN_MODE_LISTEN_ONLY (0x01U << FS65_RW_M_CAN_MODE_SHIFT)
/**
* Sleep/wake-up capability
*/
#define FS65_RW_M_CAN_MODE_SL_WU (0x02U << FS65_RW_M_CAN_MODE_SHIFT)
/**
* Normal operation mode
*/
#define FS65_RW_M_CAN_MODE_NORMAL (0x03U << FS65_RW_M_CAN_MODE_SHIFT)
/******************************************************************************/
/* LDT_AFTER_RUN_1 - Type: RW */
/******************************************************************************/
#define FS65_M_LDT_AFTER_RUN_1_ADDR 0x1AU
#define FS65_M_LDT_AFTER_RUN_1_DEFAULT 0x00U
/******************************************************************************/
/* LDT_AFTER_RUN_2 - Type: RW */
/******************************************************************************/
#define FS65_M_LDT_AFTER_RUN_2_ADDR 0x1BU
#define FS65_M_LDT_AFTER_RUN_2_DEFAULT 0x00U
/******************************************************************************/
/* LDT_WAKE_UP_1 - Type: RW */
/******************************************************************************/
#define FS65_M_LDT_WAKE_UP_1_ADDR 0x1CU
#define FS65_M_LDT_WAKE_UP_1_DEFAULT 0x00U
/******************************************************************************/
/* LDT_WAKE_UP_2 - Type: RW */
/******************************************************************************/
#define FS65_M_LDT_WAKE_UP_2_ADDR 0x1DU
#define FS65_M_LDT_WAKE_UP_2_DEFAULT 0x00U
/******************************************************************************/
/* LDT_WAKE_UP_3 - Type: RW */
/******************************************************************************/
#define FS65_M_LDT_WAKE_UP_3_ADDR 0x1EU
#define FS65_M_LDT_WAKE_UP_3_DEFAULT 0x00U
/******************************************************************************/
/* WD_ANSWER - Type: RW */
/******************************************************************************/
#define FS65_M_WD_ANSWER_ADDR 0x29U
#define FS65_M_WD_ANSWER_DEFAULT 0x40U
/**
* Report an error from the EDC of the fail-safe state machine (error detection correction)
*/
#define FS65_R_M_ERR_INT_SW_MASK 0x01U
/**
* Report an error from an internal redundant structure of the fail-safe state machine
*/
#define FS65_R_M_ERR_INT_HW_MASK 0x02U
/**
* Report a watchdog timing refresh error
*/
#define FS65_R_M_WD_BAD_TIMING_MASK 0x04U
/**
* Report an IO monitoring error
*/
#define FS65_R_M_IO_FS_G_MASK 0x08U
/**
* Report a fail-safe output failure
*/
#define FS65_R_M_FSO_G_MASK 0x10U
/**
* Report a watchdog data refresh error
*/
#define FS65_R_M_WD_BAD_DATA_MASK 0x20U
/**
* Report a fail safe event
*/
#define FS65_R_M_FSXB_MASK 0x40U
/**
* Report a reset event
*/
#define FS65_R_M_RSTB_MASK 0x80U
/**
* WD answer from the MCU, Answer = (NOT(((LFSR x 4)+6)-4))/4
*/
#define FS65_W_M_WD_ANSWER_MASK 0xFFU
/**
* Report an error from the EDC of the fail-safe state machine (error detection correction)
*/
#define FS65_R_M_ERR_INT_SW_SHIFT 0x00U
/**
* WD answer from the MCU, Answer = (NOT(((LFSR x 4)+6)-4))/4
*/
#define FS65_W_M_WD_ANSWER_SHIFT 0x00U
/**
* Report an error from an internal redundant structure of the fail-safe state machine
*/
#define FS65_R_M_ERR_INT_HW_SHIFT 0x01U
/**
* Report a watchdog timing refresh error
*/
#define FS65_R_M_WD_BAD_TIMING_SHIFT 0x02U
/**
* Report an IO monitoring error
*/
#define FS65_R_M_IO_FS_G_SHIFT 0x03U
/**
* Report a fail-safe output failure
*/
#define FS65_R_M_FSO_G_SHIFT 0x04U
/**
* Report a watchdog data refresh error
*/
#define FS65_R_M_WD_BAD_DATA_SHIFT 0x05U
/**
* Report a fail safe event
*/
#define FS65_R_M_FSXB_SHIFT 0x06U
/**
* Report a reset event
*/
#define FS65_R_M_RSTB_SHIFT 0x07U
/**
* No error
*/
#define FS65_R_M_ERR_INT_SW_NO_ERROR (0x00U << FS65_R_M_ERR_INT_SW_SHIFT)
/**
* Error detected
*/
#define FS65_R_M_ERR_INT_SW_ERROR (0x01U << FS65_R_M_ERR_INT_SW_SHIFT)
/**
* No error
*/
#define FS65_R_M_ERR_INT_HW_NO_ERROR (0x00U << FS65_R_M_ERR_INT_HW_SHIFT)
/**
* Error detected
*/
#define FS65_R_M_ERR_INT_HW_ERROR (0x01U << FS65_R_M_ERR_INT_HW_SHIFT)
/**
* WD timing refresh OK
*/
#define FS65_R_M_WD_BAD_TIMING_TIMING_OK (0x00U << FS65_R_M_WD_BAD_TIMING_SHIFT)
/**
* Wrong WD timing refresh
*/
#define FS65_R_M_WD_BAD_TIMING_WRONG_TIMING (0x01U << FS65_R_M_WD_BAD_TIMING_SHIFT)
/**
* No error
*/
#define FS65_R_M_IO_FS_G_NO_ERROR (0x00U << FS65_R_M_IO_FS_G_SHIFT)
/**
* Error detected
*/
#define FS65_R_M_IO_FS_G_ERROR (0x01U << FS65_R_M_IO_FS_G_SHIFT)
/**
* No failure
*/
#define FS65_R_M_FSO_G_NO_FAILURE (0x00U << FS65_R_M_FSO_G_SHIFT)
/**
* Failure
*/
#define FS65_R_M_FSO_G_FAILURE (0x01U << FS65_R_M_FSO_G_SHIFT)
/**
* WD data refresh ok
*/
#define FS65_R_M_WD_BAD_DATA_DATA_OK (0x00U << FS65_R_M_WD_BAD_DATA_SHIFT)
/**
* Wrong WD data refresh
*/
#define FS65_R_M_WD_BAD_DATA_WRONG_DATA (0x01U << FS65_R_M_WD_BAD_DATA_SHIFT)
/**
* No fail-safe
*/
#define FS65_R_M_FSXB_NO_FS (0x00U << FS65_R_M_FSXB_SHIFT)
/**
* Fail-safe event occurred (default state at power-up and after LPOFF as FS0B/FS1B are asserted low)
*/
#define FS65_R_M_FSXB_FSE_OCCURRED (0x01U << FS65_R_M_FSXB_SHIFT)
/**
* No reset
*/
#define FS65_R_M_RSTB_NO_RESET (0x00U << FS65_R_M_RSTB_SHIFT)
/**
* Reset occurred
*/
#define FS65_R_M_RSTB_RESET_OCCURRED (0x01U << FS65_R_M_RSTB_SHIFT)
/******************************************************************************/
/* DIAG_SF_IOS - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_SF_IOS_ADDR 0x2DU
#define FS65_M_DIAG_SF_IOS_DEFAULT 0x00U
/**
* Report an error in the IO_45 protocol
*/
#define FS65_R_M_IO_45_FAIL_MASK 0x01U
/**
* Report an error in the FCCU protocol
*/
#define FS65_R_M_IO_23_FAIL_MASK 0x02U
/**
* Report a failure on FS1B
*/
#define FS65_R_M_FS1B_DIAG_MASK 0x0CU
/**
* Report a failure on FS0B
*/
#define FS65_R_M_FS0B_DIAG_MASK 0x30U
/**
* Report a RSTB short-circuit to high
*/
#define FS65_R_M_RSTB_DIAG_MASK 0x40U
/**
* Report an external RSTB
*/
#define FS65_R_M_RSTB_EXT_MASK 0x80U
/**
* Report an error in the IO_45 protocol
*/
#define FS65_R_M_IO_45_FAIL_SHIFT 0x00U
/**
* Report an error in the FCCU protocol
*/
#define FS65_R_M_IO_23_FAIL_SHIFT 0x01U
/**
* Report a failure on FS1B
*/
#define FS65_R_M_FS1B_DIAG_SHIFT 0x02U
/**
* Report a failure on FS0B
*/
#define FS65_R_M_FS0B_DIAG_SHIFT 0x04U
/**
* Report a RSTB short-circuit to high
*/
#define FS65_R_M_RSTB_DIAG_SHIFT 0x06U
/**
* Report an external RSTB
*/
#define FS65_R_M_RSTB_EXT_SHIFT 0x07U
/**
* No error
*/
#define FS65_R_M_IO_45_FAIL_NO_ERROR (0x00U << FS65_R_M_IO_45_FAIL_SHIFT)
/**
* Error detected
*/
#define FS65_R_M_IO_45_FAIL_ERROR (0x01U << FS65_R_M_IO_45_FAIL_SHIFT)
/**
* No error
*/
#define FS65_R_M_IO_23_FAIL_NO_ERROR (0x00U << FS65_R_M_IO_23_FAIL_SHIFT)
/**
* Error detected
*/
#define FS65_R_M_IO_23_FAIL_ERROR (0x01U << FS65_R_M_IO_23_FAIL_SHIFT)
/**
* No Failure
*/
#define FS65_R_M_FS1B_DIAG_NO_FAILURE (0x01U << FS65_R_M_FS1B_DIAG_SHIFT)
/**
* Short-circuit low/open load
*/
#define FS65_R_M_FS1B_DIAG_SC_LOW (0x02U << FS65_R_M_FS1B_DIAG_SHIFT)
/**
* Short-circuit high
*/
#define FS65_R_M_FS1B_DIAG_SC_HIGH (0x03U << FS65_R_M_FS1B_DIAG_SHIFT)
/**
* No Failure
*/
#define FS65_R_M_FS0B_DIAG_NO_FAILURE (0x01U << FS65_R_M_FS0B_DIAG_SHIFT)
/**
* Short-circuit low/open load
*/
#define FS65_R_M_FS0B_DIAG_SC_LOW (0x02U << FS65_R_M_FS0B_DIAG_SHIFT)
/**
* Short-circuit high
*/
#define FS65_R_M_FS0B_DIAG_SC_HIGH (0x03U << FS65_R_M_FS0B_DIAG_SHIFT)
/**
* No Failure
*/
#define FS65_R_M_RSTB_DIAG_NO_FAILURE (0x00U << FS65_R_M_RSTB_DIAG_SHIFT)
/**
* Short-circuit high
*/
#define FS65_R_M_RSTB_DIAG_SC_HIGH (0x01U << FS65_R_M_RSTB_DIAG_SHIFT)
/**
* No external RSTB
*/
#define FS65_R_M_RSTB_EXT_NO (0x00U << FS65_R_M_RSTB_EXT_SHIFT)
/**
* External RSTB
*/
#define FS65_R_M_RSTB_EXT_EXTERNAL (0x01U << FS65_R_M_RSTB_EXT_SHIFT)
/******************************************************************************/
/* WD_COUNTER - Type: R */
/******************************************************************************/
#define FS65_M_WD_COUNTER_ADDR 0x2EU
#define FS65_M_WD_COUNTER_DEFAULT 0x00U
/**
* Report the value of the watchdog refresh counter from 0 to 6 (7 generate a decrease of the FLT_ERR_CNT and this
* counter is reset to 0)
*/
#define FS65_R_M_WD_RFR_MASK 0x0EU
/**
* Report the value of the watchdog error counter from 0 to 5 (6 generate an increase of the FLT_ERR_CNT and this
* counter is reset to 0)
*/
#define FS65_R_M_WD_ERR_MASK 0xE0U
/**
* Report the value of the watchdog refresh counter from 0 to 6 (7 generate a decrease of the FLT_ERR_CNT and this
* counter is reset to 0)
*/
#define FS65_R_M_WD_RFR_SHIFT 0x01U
/**
* Report the value of the watchdog error counter from 0 to 5 (6 generate an increase of the FLT_ERR_CNT and this
* counter is reset to 0)
*/
#define FS65_R_M_WD_ERR_SHIFT 0x05U
/******************************************************************************/
/* DIAG_SF_ERR - Type: R */
/******************************************************************************/
#define FS65_M_DIAG_SF_ERR_ADDR 0x2FU
#define FS65_M_DIAG_SF_ERR_DEFAULT 0x20U
/**
* Report an undervoltage on FCRBM
*/
#define FS65_R_M_FCRBM_UV_MASK 0x01U
/**
* Report an overvoltage on FCRBM
*/
#define FS65_R_M_FCRBM_OV_MASK 0x02U
/**
* Report an overvoltage on V2P5 main digital regulator
*/
#define FS65_R_M_V2P5_M_D_OV_MASK 0x04U
/**
* Report an overvoltage on V2P5 main analog regulator
*/
#define FS65_R_M_V2P5_M_A_OV_MASK 0x08U
/**
* Report the value of the fault error counter
*/
#define FS65_R_M_FLT_ERR_MASK 0xE0U
/**
* Report an undervoltage on FCRBM
*/
#define FS65_R_M_FCRBM_UV_SHIFT 0x00U
/**
* Report an overvoltage on FCRBM
*/
#define FS65_R_M_FCRBM_OV_SHIFT 0x01U
/**
* Report an overvoltage on V2P5 main digital regulator
*/
#define FS65_R_M_V2P5_M_D_OV_SHIFT 0x02U
/**
* Report an overvoltage on V2P5 main analog regulator
*/
#define FS65_R_M_V2P5_M_A_OV_SHIFT 0x03U
/**
* Report the value of the fault error counter
*/
#define FS65_R_M_FLT_ERR_SHIFT 0x05U
/**
* No undervoltage (FB_Core - FCRBM > -150 mV)
*/
#define FS65_R_M_FCRBM_UV_NO_UNDERVOLTAGE (0x00U << FS65_R_M_FCRBM_UV_SHIFT)
/**
* Undervoltage detected (FB_Core - FCRBM < -150 mV)
*/
#define FS65_R_M_FCRBM_UV_UNDERVOLTAGE (0x01U << FS65_R_M_FCRBM_UV_SHIFT)
/**
* No overvoltage (FB_Core - FCRBM < 150 mV)
*/
#define FS65_R_M_FCRBM_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_FCRBM_OV_SHIFT)
/**
* Overvoltage detected (FB_Core - FCRBM > 150 mV)
*/
#define FS65_R_M_FCRBM_OV_OVERVOLTAGE (0x01U << FS65_R_M_FCRBM_OV_SHIFT)
/**
* No overvoltage (V2P5_M_D < V2P5_M_D_OV)
*/
#define FS65_R_M_V2P5_M_D_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_V2P5_M_D_OV_SHIFT)
/**
* Overvoltage detected (V2P5_M_D > V2P5_M_D_OV)
*/
#define FS65_R_M_V2P5_M_D_OV_OVERVOLTAGE (0x01U << FS65_R_M_V2P5_M_D_OV_SHIFT)
/**
* No overvoltage (V2P5_M_A < V2P5_M_A_OV)
*/
#define FS65_R_M_V2P5_M_A_OV_NO_OVERVOLTAGE (0x00U << FS65_R_M_V2P5_M_A_OV_SHIFT)
/**
* Overvoltage detected (V2P5_M_A > V2P5_M_A_OV)
*/
#define FS65_R_M_V2P5_M_A_OV_OVERVOLTAGE (0x01U << FS65_R_M_V2P5_M_A_OV_SHIFT)
/******************************************************************************/
/* DEVICE_ID_FS - Type: R */
/******************************************************************************/
#define FS65_M_DEVICE_ID_FS_ADDR 0x34U
#define FS65_M_DEVICE_ID_FS_DEFAULT 0x00U
/**
* Report the FS1B function availability (depends on part number)
*/
#define FS65_R_M_FS1_MASK 0x01U
/**
* Report the deep fail-safe hardware configuration (fail-safe logic)
*/
#define FS65_R_M_DFS_HW2_MASK 0x02U
/**
* Report the FS1B function availability (depends on part number)
*/
#define FS65_R_M_FS1_SHIFT 0x00U
/**
* Report the deep fail-safe hardware configuration (fail-safe logic)
*/
#define FS65_R_M_DFS_HW2_SHIFT 0x01U
/**
* Disabled
*/
#define FS65_R_M_FS1_DISABLED (0x00U << FS65_R_M_FS1_SHIFT)
/**
* Enabled
*/
#define FS65_R_M_FS1_ENABLE (0x01U << FS65_R_M_FS1_SHIFT)
/**
* Deep fail-safe disable
*/
#define FS65_R_M_DFS_HW2_DISABLE (0x00U << FS65_R_M_DFS_HW2_SHIFT)
/**
* Deep fail-safe enable
*/
#define FS65_R_M_DFS_HW2_ENABLE (0x01U << FS65_R_M_DFS_HW2_SHIFT)
/******************************************************************************/
/* BIST - Type: RW */
/******************************************************************************/
#define FS65_FS_BIST_ADDR 0x22U
#define FS65_FS_BIST_DEFAULT 0x09U
/**
* Diagnostic of analog BIST1 (automatically executed)
*/
#define FS65_R_FS_ABIST1_OK_MASK 0x01U
/**
* Diagnostic of VAUX Analog BIST2 (executed on demand)
*/
#define FS65_R_FS_ABIST2_VAUX_OK_MASK 0x02U
/**
* Diagnostic of FS1B Analog BIST2 (executed on demand)
*/
#define FS65_R_FS_ABIST2_FS1B_OK_MASK 0x04U
/**
* Diagnostic of fail-safe logic BIST (automatically executed)
*/
#define FS65_R_FS_LBIST_OK_MASK 0x08U
/**
* Request ABIST execution on VAUX
*/
#define FS65_W_FS_ABIST2_VAUX_MASK 0x20U
/**
* Request ABIST execution on FS1B
*/
#define FS65_W_FS_ABIST2_FS1B_MASK 0x40U
/**
* Diagnostic of analog BIST1 (automatically executed)
*/
#define FS65_R_FS_ABIST1_OK_SHIFT 0x00U
/**
* Diagnostic of VAUX Analog BIST2 (executed on demand)
*/
#define FS65_R_FS_ABIST2_VAUX_OK_SHIFT 0x01U
/**
* Diagnostic of FS1B Analog BIST2 (executed on demand)
*/
#define FS65_R_FS_ABIST2_FS1B_OK_SHIFT 0x02U
/**
* Diagnostic of fail-safe logic BIST (automatically executed)
*/
#define FS65_R_FS_LBIST_OK_SHIFT 0x03U
/**
* Request ABIST execution on VAUX
*/
#define FS65_W_FS_ABIST2_VAUX_SHIFT 0x05U
/**
* Request ABIST execution on FS1B
*/
#define FS65_W_FS_ABIST2_FS1B_SHIFT 0x06U
/**
* ABIST1 fail
*/
#define FS65_R_FS_ABIST1_OK_FAIL (0x00U << FS65_R_FS_ABIST1_OK_SHIFT)
/**
* ABIST1 pass
*/
#define FS65_R_FS_ABIST1_OK_PASS (0x01U << FS65_R_FS_ABIST1_OK_SHIFT)
/**
* VAUX ABIST fail or not executed
*/
#define FS65_R_FS_ABIST2_VAUX_OK_FAIL (0x00U << FS65_R_FS_ABIST2_VAUX_OK_SHIFT)
/**
* VAUX ABIST pass
*/
#define FS65_R_FS_ABIST2_VAUX_OK_PASS (0x01U << FS65_R_FS_ABIST2_VAUX_OK_SHIFT)
/**
* FS1B ABIST fail or not executed
*/
#define FS65_R_FS_ABIST2_FS1B_OK_FAIL (0x00U << FS65_R_FS_ABIST2_FS1B_OK_SHIFT)
/**
* FS1B ABIST pass
*/
#define FS65_R_FS_ABIST2_FS1B_OK_PASS (0x01U << FS65_R_FS_ABIST2_FS1B_OK_SHIFT)
/**
* LBIST fail
*/
#define FS65_R_FS_LBIST_OK_FAIL (0x00U << FS65_R_FS_LBIST_OK_SHIFT)
/**
* LBIST pass
*/
#define FS65_R_FS_LBIST_OK_PASS (0x01U << FS65_R_FS_LBIST_OK_SHIFT)
/**
* No action
*/
#define FS65_W_FS_ABIST2_VAUX_NO_ACTION (0x00U << FS65_W_FS_ABIST2_VAUX_SHIFT)
/**
* Launch ABIST on VAUX
*/
#define FS65_W_FS_ABIST2_VAUX_ABIST_VAUX (0x01U << FS65_W_FS_ABIST2_VAUX_SHIFT)
/**
* No action
*/
#define FS65_W_FS_ABIST2_FS1B_NO_ACTION (0x00U << FS65_W_FS_ABIST2_FS1B_SHIFT)
/**
* Launch ABIST on FS1B
*/
#define FS65_W_FS_ABIST2_FS1B_ABIST_FS1B (0x01U << FS65_W_FS_ABIST2_FS1B_SHIFT)
/******************************************************************************/
/* RELEASE_FSXB - Type: RW */
/******************************************************************************/
#define FS65_FS_RELEASE_FSXB_ADDR 0x2AU
#define FS65_FS_RELEASE_FSXB_DEFAULT 0x01U
/**
* Sense of RSTB pad
*/
#define FS65_R_FS_RSTB_SNS_MASK 0x01U
/**
* Sense of FS0B pad
*/
#define FS65_R_FS_FS0B_SNS_MASK 0x02U
/**
* Sense of FS1B pad
*/
#define FS65_R_FS_FS1B_SNS_MASK 0x04U
/**
* Secured 8 bits word to release the FS0B and FS1B pins, depend on LFSR_out value and calculation
*/
#define FS65_W_FS_RELEASE_FSXB_MASK 0xFFU
/**
* Sense of RSTB pad
*/
#define FS65_R_FS_RSTB_SNS_SHIFT 0x00U
/**
* Secured 8 bits word to release the FS0B and FS1B pins, depend on LFSR_out value and calculation
*/
#define FS65_W_FS_RELEASE_FSXB_SHIFT 0x00U
/**
* Sense of FS0B pad
*/
#define FS65_R_FS_FS0B_SNS_SHIFT 0x01U
/**
* Sense of FS1B pad
*/
#define FS65_R_FS_FS1B_SNS_SHIFT 0x02U
/**
* RSTB pad sense low
*/
#define FS65_R_FS_RSTB_SNS_LOW (0x00U << FS65_R_FS_RSTB_SNS_SHIFT)
/**
* RSTB pad sense high
*/
#define FS65_R_FS_RSTB_SNS_HIGH (0x01U << FS65_R_FS_RSTB_SNS_SHIFT)
/**
* FS0B pad sense low
*/
#define FS65_R_FS_FS0B_SNS_LOW (0x00U << FS65_R_FS_FS0B_SNS_SHIFT)
/**
* FS0B pad sense high
*/
#define FS65_R_FS_FS0B_SNS_HIGH (0x01U << FS65_R_FS_FS0B_SNS_SHIFT)
/**
* FS1B pad sense low
*/
#define FS65_R_FS_FS1B_SNS_LOW (0x00U << FS65_R_FS_FS1B_SNS_SHIFT)
/**
* FS1B pad sense high
*/
#define FS65_R_FS_FS1B_SNS_HIGH (0x01U << FS65_R_FS_FS1B_SNS_SHIFT)
/******************************************************************************/
/* SF_OUTPUT_REQUEST - Type: RW */
/******************************************************************************/
#define FS65_FS_SF_OUTPUT_REQUEST_ADDR 0x2BU
#define FS65_FS_SF_OUTPUT_REQUEST_DEFAULT 0x01U
/**
* Sense of RSTB driver command from fail-safe logic
*/
#define FS65_R_FS_RSTB_DRV_MASK 0x01U
/**
* Sense of FS0B driver command from fail-safe logic
*/
#define FS65_R_FS_FS0B_DRV_MASK 0x02U
/**
* Sense of FS1B driver command from backup delay (analog)
*/
#define FS65_R_FS_FS1B_DLY_DRV_MASK 0x04U
/**
* Sense of FS1B driver command from fail-safe logic (digital)
*/
#define FS65_R_FS_FS1B_DRV_MASK 0x08U
/**
* Request a RSTB low pulse
*/
#define FS65_W_FS_RSTB_REQ_MASK 0x10U
/**
* Request FS0B to be asserted low
*/
#define FS65_W_FS_FS0B_REQ_MASK 0x20U
/**
* Request activation of FS1B backup delay (open/close switch S1)
*/
#define FS65_W_FS_FS1B_DLY_REQ_MASK 0x40U
/**
* Request FS1B to be asserted low
*/
#define FS65_W_FS_FS1B_REQ_MASK 0x80U
/**
* Sense of RSTB driver command from fail-safe logic
*/
#define FS65_R_FS_RSTB_DRV_SHIFT 0x00U
/**
* Sense of FS0B driver command from fail-safe logic
*/
#define FS65_R_FS_FS0B_DRV_SHIFT 0x01U
/**
* Sense of FS1B driver command from backup delay (analog)
*/
#define FS65_R_FS_FS1B_DLY_DRV_SHIFT 0x02U
/**
* Sense of FS1B driver command from fail-safe logic (digital)
*/
#define FS65_R_FS_FS1B_DRV_SHIFT 0x03U
/**
* Request a RSTB low pulse
*/
#define FS65_W_FS_RSTB_REQ_SHIFT 0x04U
/**
* Request FS0B to be asserted low
*/
#define FS65_W_FS_FS0B_REQ_SHIFT 0x05U
/**
* Request activation of FS1B backup delay (open/close switch S1)
*/
#define FS65_W_FS_FS1B_DLY_REQ_SHIFT 0x06U
/**
* Request FS1B to be asserted low
*/
#define FS65_W_FS_FS1B_REQ_SHIFT 0x07U
/**
* RSTB driver sense low
*/
#define FS65_R_FS_RSTB_DRV_LOW (0x00U << FS65_R_FS_RSTB_DRV_SHIFT)
/**
* RSTB driver sense high
*/
#define FS65_R_FS_RSTB_DRV_HIGH (0x01U << FS65_R_FS_RSTB_DRV_SHIFT)
/**
* FS0B driver sense low
*/
#define FS65_R_FS_FS0B_DRV_LOW (0x00U << FS65_R_FS_FS0B_DRV_SHIFT)
/**
* FS0B driver sense high
*/
#define FS65_R_FS_FS0B_DRV_HIGH (0x01U << FS65_R_FS_FS0B_DRV_SHIFT)
/**
* FS1B analog driver sense low
*/
#define FS65_R_FS_FS1B_DLY_DRV_FS1B_LOW (0x00U << FS65_R_FS_FS1B_DLY_DRV_SHIFT)
/**
* FS1B analog driver sense high
*/
#define FS65_R_FS_FS1B_DLY_DRV_FS1B_HIGH (0x01U << FS65_R_FS_FS1B_DLY_DRV_SHIFT)
/**
* FS1B digital driver sense low
*/
#define FS65_R_FS_FS1B_DRV_FS1B_LOW (0x00U << FS65_R_FS_FS1B_DRV_SHIFT)
/**
* FS1B digital driver sense high
*/
#define FS65_R_FS_FS1B_DRV_FS1B_HIGH (0x01U << FS65_R_FS_FS1B_DRV_SHIFT)
/**
* No request
*/
#define FS65_W_FS_RSTB_REQ_NO_REQUEST (0x00U << FS65_W_FS_RSTB_REQ_SHIFT)
/**
* Request a RSTB low pulse
*/
#define FS65_W_FS_RSTB_REQ_RSTB_REQ (0x01U << FS65_W_FS_RSTB_REQ_SHIFT)
/**
* No request
*/
#define FS65_W_FS_FS0B_REQ_NO_REQUEST (0x00U << FS65_W_FS_FS0B_REQ_SHIFT)
/**
* Request FS0B assertion
*/
#define FS65_W_FS_FS0B_REQ_FS0B_REQ (0x01U << FS65_W_FS_FS0B_REQ_SHIFT)
/**
* No request (close S1)
*/
#define FS65_W_FS_FS1B_DLY_REQ_NO_REQUEST (0x00U << FS65_W_FS_FS1B_DLY_REQ_SHIFT)
/**
* Request FS1B assertion with tDELAY controlled by the backup delay (open S1)
*/
#define FS65_W_FS_FS1B_DLY_REQ_FS1B_REQ (0x01U << FS65_W_FS_FS1B_DLY_REQ_SHIFT)
/**
* No request
*/
#define FS65_W_FS_FS1B_REQ_NO_REQUEST (0x00U << FS65_W_FS_FS1B_REQ_SHIFT)
/**
* Request FS1B assertion with immediate assertion, no delay
*/
#define FS65_W_FS_FS1B_REQ_FS1B_REQ (0x01U << FS65_W_FS_FS1B_REQ_SHIFT)
/******************************************************************************/
/* INIT_WU1 - Type: RW */
/******************************************************************************/
#define FS65_M_INIT_WU1_ADDR 0x02U
#define FS65_M_INIT_WU1_DEFAULT 0x40U
/**
* IO_4 wake-up configuration
*/
#define FS65_RW_M_WU_IO4_MASK 0x03U
/**
* IO_3 wake-up configuration
*/
#define FS65_RW_M_WU_IO3_MASK 0x0CU
/**
* IO_2 wake-up configuration
*/
#define FS65_RW_M_WU_IO2_MASK 0x30U
/**
* IO_0 wake-up configuration
*/
#define FS65_RW_M_WU_IO0_MASK 0xC0U
/**
* IO_4 wake-up configuration
*/
#define FS65_RW_M_WU_IO4_SHIFT 0x00U
/**
* IO_3 wake-up configuration
*/
#define FS65_RW_M_WU_IO3_SHIFT 0x02U
/**
* IO_2 wake-up configuration
*/
#define FS65_RW_M_WU_IO2_SHIFT 0x04U
/**
* IO_0 wake-up configuration
*/
#define FS65_RW_M_WU_IO0_SHIFT 0x06U
/**
* NO wake-up capability
*/
#define FS65_RW_M_WU_IO4_NO_WAKEUP (0x00U << FS65_RW_M_WU_IO4_SHIFT)
/**
* Wake-up on rising edge - or high level
*/
#define FS65_RW_M_WU_IO4_RISING_EDGE (0x01U << FS65_RW_M_WU_IO4_SHIFT)
/**
* Wake-up on falling edge - or low level
*/
#define FS65_RW_M_WU_IO4_FALLING_EDGE (0x02U << FS65_RW_M_WU_IO4_SHIFT)
/**
* Wake-up on any edge
*/
#define FS65_RW_M_WU_IO4_ANY_EDGE (0x03U << FS65_RW_M_WU_IO4_SHIFT)
/**
* NO wake-up capability
*/
#define FS65_RW_M_WU_IO3_NO_WAKEUP (0x00U << FS65_RW_M_WU_IO3_SHIFT)
/**
* Wake-up on rising edge - or high level
*/
#define FS65_RW_M_WU_IO3_RISING_EDGE (0x01U << FS65_RW_M_WU_IO3_SHIFT)
/**
* Wake-up on falling edge - or low level
*/
#define FS65_RW_M_WU_IO3_FALLING_EDGE (0x02U << FS65_RW_M_WU_IO3_SHIFT)
/**
* Wake-up on any edge
*/
#define FS65_RW_M_WU_IO3_ANY_EDGE (0x03U << FS65_RW_M_WU_IO3_SHIFT)
/**
* NO wake-up capability
*/
#define FS65_RW_M_WU_IO2_NO_WAKEUP (0x00U << FS65_RW_M_WU_IO2_SHIFT)
/**
* Wake-up on rising edge - or high level
*/
#define FS65_RW_M_WU_IO2_RISING_EDGE (0x01U << FS65_RW_M_WU_IO2_SHIFT)
/**
* Wake-up on falling edge - or low level
*/
#define FS65_RW_M_WU_IO2_FALLING_EDGE (0x02U << FS65_RW_M_WU_IO2_SHIFT)
/**
* Wake-up on any edge
*/
#define FS65_RW_M_WU_IO2_ANY_EDGE (0x03U << FS65_RW_M_WU_IO2_SHIFT)
/**
* NO wake-up capability
*/
#define FS65_RW_M_WU_IO0_NO_WAKEUP (0x00U << FS65_RW_M_WU_IO0_SHIFT)
/**
* Wake-up on rising edge - or high level
*/
#define FS65_RW_M_WU_IO0_RISING_EDGE (0x01U << FS65_RW_M_WU_IO0_SHIFT)
/**
* Wake-up on falling edge - or low level
*/
#define FS65_RW_M_WU_IO0_FALLING_EDGE (0x02U << FS65_RW_M_WU_IO0_SHIFT)
/**
* Wake-up on any edge
*/
#define FS65_RW_M_WU_IO0_ANY_EDGE (0x03U << FS65_RW_M_WU_IO0_SHIFT)
/******************************************************************************/
/* INIT_WU2 - Type: RW */
/******************************************************************************/
#define FS65_M_INIT_WU2_ADDR 0x03U
#define FS65_M_INIT_WU2_DEFAULT 0x00U
/**
* Configure the LIN slew rate
*/
#define FS65_RW_M_LIN_SR_MASK 0x03U
/**
* To comply with J2602 standard. Recessive mode when VSUP < 7.0 V
*/
#define FS65_RW_M_LIN_J2602_DIS_MASK 0x04U
/**
* Define the CAN wake-up timeout (when CAN_WU_CONF = 0)
*/
#define FS65_RW_M_CAN_WU_TO_MASK 0x10U
/**
* Define CAN behavior when FS1B is asserted low
*/
#define FS65_RW_M_CAN_DIS_CFG_MASK 0x20U
/**
* IO_5 wake-up configuration
*/
#define FS65_RW_M_WU_IO5_MASK 0xC0U
/**
* Configure the LIN slew rate
*/
#define FS65_RW_M_LIN_SR_SHIFT 0x00U
/**
* To comply with J2602 standard. Recessive mode when VSUP < 7.0 V
*/
#define FS65_RW_M_LIN_J2602_DIS_SHIFT 0x02U
/**
* Define the CAN wake-up timeout (when CAN_WU_CONF = 0)
*/
#define FS65_RW_M_CAN_WU_TO_SHIFT 0x04U
/**
* Define CAN behavior when FS1B is asserted low
*/
#define FS65_RW_M_CAN_DIS_CFG_SHIFT 0x05U
/**
* IO_5 wake-up configuration
*/
#define FS65_RW_M_WU_IO5_SHIFT 0x06U
/**
* 20 kbits/s
*/
#define FS65_RW_M_LIN_SR_20KBITS (0x00U << FS65_RW_M_LIN_SR_SHIFT)
/**
* 10 kbits/s
*/
#define FS65_RW_M_LIN_SR_10KBITS (0x01U << FS65_RW_M_LIN_SR_SHIFT)
/**
* Fast baud rate (Max: 100 kbits/s)
*/
#define FS65_RW_M_LIN_SR_FAST_RATE (0x02U << FS65_RW_M_LIN_SR_SHIFT)
/**
* Compliant with J2602 standard
*/
#define FS65_RW_M_LIN_J2602_DIS_COMPLIANT (0x00U << FS65_RW_M_LIN_J2602_DIS_SHIFT)
/**
* Not compliant with J2602 standard
*/
#define FS65_RW_M_LIN_J2602_DIS_NOT_COMPLIANT (0x01U << FS65_RW_M_LIN_J2602_DIS_SHIFT)
/**
* 120 us
*/
#define FS65_RW_M_CAN_WU_TO_120US (0x00U << FS65_RW_M_CAN_WU_TO_SHIFT)
/**
* 2.8 ms
*/
#define FS65_RW_M_CAN_WU_TO_2_8MS (0x01U << FS65_RW_M_CAN_WU_TO_SHIFT)
/**
* CAN in Rx only mode (when FS1B_CAN_ IMPACT = 1 in INIT_FAULT register)
*/
#define FS65_RW_M_CAN_DIS_CFG_RX_ONLY (0x00U << FS65_RW_M_CAN_DIS_CFG_SHIFT)
/**
* CAN in sleep mode (when FS1B_CAN_ IMPACT = 1 in INIT_FAULT register)
*/
#define FS65_RW_M_CAN_DIS_CFG_SLEEP (0x01U << FS65_RW_M_CAN_DIS_CFG_SHIFT)
/**
* NO wake-up capability
*/
#define FS65_RW_M_WU_IO5_NO_WAKEUP (0x00U << FS65_RW_M_WU_IO5_SHIFT)
/**
* Wake-up on rising edge - or high level
*/
#define FS65_RW_M_WU_IO5_RISING_EDGE (0x01U << FS65_RW_M_WU_IO5_SHIFT)
/**
* Wake-up on falling edge - or low level
*/
#define FS65_RW_M_WU_IO5_FALLING_EDGE (0x02U << FS65_RW_M_WU_IO5_SHIFT)
/**
* Wake-up on any edge
*/
#define FS65_RW_M_WU_IO5_ANY_EDGE (0x03U << FS65_RW_M_WU_IO5_SHIFT)
/******************************************************************************/
/* INIT_INH_INT - Type: RW */
/******************************************************************************/
#define FS65_M_INIT_INH_INT_ADDR 0x05U
#define FS65_M_INIT_INH_INT_DEFAULT 0x06U
/**
* Inhibit the interrupt pulse for IO_0 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_0_MASK 0x01U
/**
* Inhibit the interrupt pulse for IO_2 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_2_MASK 0x02U
/**
* Inhibit the interrupt pulse for IO_3 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_3_MASK 0x04U
/**
* Inhibit the interrupt pulse for IO_4 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_4_MASK 0x08U
/**
* Inhibit the interrupt pulse for IO_5 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_5_MASK 0x10U
/**
* Inhibit the interrupt pulse for IO_0 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_0_SHIFT 0x00U
/**
* Inhibit the interrupt pulse for IO_2 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_2_SHIFT 0x01U
/**
* Inhibit the interrupt pulse for IO_3 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_3_SHIFT 0x02U
/**
* Inhibit the interrupt pulse for IO_4 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_4_SHIFT 0x03U
/**
* Inhibit the interrupt pulse for IO_5 (masked in IO_G)
*/
#define FS65_RW_M_INT_INH_5_SHIFT 0x04U
/**
* INT not masked
*/
#define FS65_RW_M_INT_INH_0_NOT_MASKED (0x00U << FS65_RW_M_INT_INH_0_SHIFT)
/**
* INT masked
*/
#define FS65_RW_M_INT_INH_0_MASKED (0x01U << FS65_RW_M_INT_INH_0_SHIFT)
/**
* INT not masked
*/
#define FS65_RW_M_INT_INH_2_NOT_MASKED (0x00U << FS65_RW_M_INT_INH_2_SHIFT)
/**
* INT masked
*/
#define FS65_RW_M_INT_INH_2_MASKED (0x01U << FS65_RW_M_INT_INH_2_SHIFT)
/**
* INT not masked
*/
#define FS65_RW_M_INT_INH_3_NOT_MASKED (0x00U << FS65_RW_M_INT_INH_3_SHIFT)
/**
* INT masked
*/
#define FS65_RW_M_INT_INH_3_MASKED (0x01U << FS65_RW_M_INT_INH_3_SHIFT)
/**
* INT not masked
*/
#define FS65_RW_M_INT_INH_4_NOT_MASKED (0x00U << FS65_RW_M_INT_INH_4_SHIFT)
/**
* INT masked
*/
#define FS65_RW_M_INT_INH_4_MASKED (0x01U << FS65_RW_M_INT_INH_4_SHIFT)
/**
* INT not masked
*/
#define FS65_RW_M_INT_INH_5_NOT_MASKED (0x00U << FS65_RW_M_INT_INH_5_SHIFT)
/**
* INT masked
*/
#define FS65_RW_M_INT_INH_5_MASKED (0x01U << FS65_RW_M_INT_INH_5_SHIFT)
/******************************************************************************/
/* INIT_FS1B_TIMING - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_FS1B_TIMING_ADDR 0x21U
#define FS65_FS_INIT_FS1B_TIMING_DEFAULT 0x06U
/**
* FS1B timing range factor x1(FS1B_TIME_RANGE bit = 0), FS1B timing range factor x8(FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_MASK 0x0FU
/**
* FS1B timing range factor x1(FS1B_TIME_RANGE bit = 0), FS1B timing range factor x8(FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_MASK 0xF0U
/**
* FS1B timing range factor x1(FS1B_TIME_RANGE bit = 0), FS1B timing range factor x8(FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_SHIFT 0x00U
/**
* FS1B timing range factor x1(FS1B_TIME_RANGE bit = 0), FS1B timing range factor x8(FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_SHIFT 0x04U
/**
* 0
*/
#define FS65_R_FS_FS1B_TIME_0_0 (0x00U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 10 ms (FS1B_TIME_RANGE bit = 0) | 80 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_10MS_80MS (0x01U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 13 ms (FS1B_TIME_RANGE bit = 0) | 104 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_13_104MS (0x02U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 17 ms (FS1B_TIME_RANGE bit = 0) | 135 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_17_135MS (0x03U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 22 ms (FS1B_TIME_RANGE bit = 0) | 176 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_22_176MS (0x04U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 29 ms (FS1B_TIME_RANGE bit = 0) | 228 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_29_228MS (0x05U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 37 ms (FS1B_TIME_RANGE bit = 0) | 297 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_37_297MS (0x06U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 48 ms (FS1B_TIME_RANGE bit = 0) | 386 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_48_386MS (0x07U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 63 ms (FS1B_TIME_RANGE bit = 0) | 502 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_63_502MS (0x08U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 82 ms (FS1B_TIME_RANGE bit = 0) | 653 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_82_653MS (0x09U << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 106 ms (FS1B_TIME_RANGE bit = 0) | 848 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_106_848MS (0x0AU << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 138 ms (FS1B_TIME_RANGE bit = 0) | 1103 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_138_1103MS (0x0BU << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 179 ms (FS1B_TIME_RANGE bit = 0) | 1434 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_179_1434MS (0x0CU << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 233 ms (FS1B_TIME_RANGE bit = 0) | 1864 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_233_1864MS (0x0DU << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 303 ms (FS1B_TIME_RANGE bit = 0) | 2423 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_303_2423MS (0x0EU << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 394 ms (FS1B_TIME_RANGE bit = 0) | 3150 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_R_FS_FS1B_TIME_394_3150MS (0x0FU << FS65_R_FS_FS1B_TIME_SHIFT)
/**
* 0
*/
#define FS65_W_FS_FS1B_TIME_0_0 (0x00U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 10 ms (FS1B_TIME_RANGE bit = 0) | 80 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_10MS_80MS (0x01U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 13 ms (FS1B_TIME_RANGE bit = 0) | 104 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_13_104MS (0x02U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 17 ms (FS1B_TIME_RANGE bit = 0) | 135 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_17_135MS (0x03U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 22 ms (FS1B_TIME_RANGE bit = 0) | 176 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_22_176MS (0x04U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 29 ms (FS1B_TIME_RANGE bit = 0) | 228 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_29_228MS (0x05U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 37 ms (FS1B_TIME_RANGE bit = 0) | 297 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_37_297MS (0x06U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 48 ms (FS1B_TIME_RANGE bit = 0) | 386 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_48_386MS (0x07U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 63 ms (FS1B_TIME_RANGE bit = 0) | 502 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_63_502MS (0x08U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 82 ms (FS1B_TIME_RANGE bit = 0) | 653 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_82_653MS (0x09U << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 106 ms (FS1B_TIME_RANGE bit = 0) | 848 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_106_848MS (0x0AU << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 138 ms (FS1B_TIME_RANGE bit = 0) | 1103 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_138_1103MS (0x0BU << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 179 ms (FS1B_TIME_RANGE bit = 0) | 1434 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_179_1434MS (0x0CU << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 233 ms (FS1B_TIME_RANGE bit = 0) | 1864 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_233_1864MS (0x0DU << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 303 ms (FS1B_TIME_RANGE bit = 0) | 2423 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_303_2423MS (0x0EU << FS65_W_FS_FS1B_TIME_SHIFT)
/**
* 394 ms (FS1B_TIME_RANGE bit = 0) | 3150 ms (FS1B_TIME_RANGE bit = 1)
*/
#define FS65_W_FS_FS1B_TIME_394_3150MS (0x0FU << FS65_W_FS_FS1B_TIME_SHIFT)
/******************************************************************************/
/* INIT_SUPERVISOR - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_SUPERVISOR_ADDR 0x23U
#define FS65_FS_INIT_SUPERVISOR_DEFAULT 0x00U
/**
* Configure the FS1B timing range factor x1 or x8
*/
#define FS65_R_FS_FS1B_TIME_RANGE_MASK 0x01U
/**
* Configure the VAUX undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_R_FS_VAUX_5D_MASK 0x02U
/**
* Configure the VCCA undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_R_FS_VCCA_5D_MASK 0x04U
/**
* Configure the VCORE undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_R_FS_VCORE_5D_MASK 0x08U
/**
* Configure the FS1B timing range factor x1 or x8
*/
#define FS65_W_FS_FS1B_TIME_RANGE_MASK 0x10U
/**
* Configure the VAUX undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_W_FS_VAUX_5D_MASK 0x20U
/**
* Configure the VCCA undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_W_FS_VCCA_5D_MASK 0x40U
/**
* Configure the VCORE undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_W_FS_VCORE_5D_MASK 0x80U
/**
* Configure the FS1B timing range factor x1 or x8
*/
#define FS65_R_FS_FS1B_TIME_RANGE_SHIFT 0x00U
/**
* Configure the VAUX undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_R_FS_VAUX_5D_SHIFT 0x01U
/**
* Configure the VCCA undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_R_FS_VCCA_5D_SHIFT 0x02U
/**
* Configure the VCORE undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_R_FS_VCORE_5D_SHIFT 0x03U
/**
* Configure the FS1B timing range factor x1 or x8
*/
#define FS65_W_FS_FS1B_TIME_RANGE_SHIFT 0x04U
/**
* Configure the VAUX undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_W_FS_VAUX_5D_SHIFT 0x05U
/**
* Configure the VCCA undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_W_FS_VCCA_5D_SHIFT 0x06U
/**
* Configure the VCORE undervoltage in degraded mode. Only valid for 5.0 V
*/
#define FS65_W_FS_VCORE_5D_SHIFT 0x07U
/**
* x1 timing range factor
*/
#define FS65_R_FS_FS1B_TIME_RANGE_X1 (0x00U << FS65_R_FS_FS1B_TIME_RANGE_SHIFT)
/**
* x8 timing range factor
*/
#define FS65_R_FS_FS1B_TIME_RANGE_X8 (0x01U << FS65_R_FS_FS1B_TIME_RANGE_SHIFT)
/**
* Normal 5.0 V undervoltage detection threshold (VAUX_UV_5)
*/
#define FS65_R_FS_VAUX_5D_NORMAL (0x00U << FS65_R_FS_VAUX_5D_SHIFT)
/**
* Degraded mode; lower undervoltage detection threshold applied (VAUX_UV_5D)
*/
#define FS65_R_FS_VAUX_5D_DEGRADED (0x01U << FS65_R_FS_VAUX_5D_SHIFT)
/**
* Normal 5.0 V undervoltage detection threshold (VCCA_UV_5)
*/
#define FS65_R_FS_VCCA_5D_NORMAL (0x00U << FS65_R_FS_VCCA_5D_SHIFT)
/**
* Degraded mode, lower undervoltage detection threshold applied (VCCA_UV_D)
*/
#define FS65_R_FS_VCCA_5D_DEGRADED (0x01U << FS65_R_FS_VCCA_5D_SHIFT)
/**
* Normal 5.0 V undervoltage detection threshold (VCORE_FB_UV)
*/
#define FS65_R_FS_VCORE_5D_NORMAL (0x00U << FS65_R_FS_VCORE_5D_SHIFT)
/**
* Degraded mode, lower undervoltage detection threshold applied (VCORE_FB_UV_D)
*/
#define FS65_R_FS_VCORE_5D_DEGRADED (0x01U << FS65_R_FS_VCORE_5D_SHIFT)
/**
* x1 timing range factor
*/
#define FS65_W_FS_FS1B_TIME_RANGE_X1 (0x00U << FS65_W_FS_FS1B_TIME_RANGE_SHIFT)
/**
* x8 timing range factor
*/
#define FS65_W_FS_FS1B_TIME_RANGE_X8 (0x01U << FS65_W_FS_FS1B_TIME_RANGE_SHIFT)
/**
* Normal 5.0 V undervoltage detection threshold (VAUX_UV_5)
*/
#define FS65_W_FS_VAUX_5D_NORMAL (0x00U << FS65_W_FS_VAUX_5D_SHIFT)
/**
* Degraded mode; lower undervoltage detection threshold applied (VAUX_UV_5D)
*/
#define FS65_W_FS_VAUX_5D_DEGRADED (0x01U << FS65_W_FS_VAUX_5D_SHIFT)
/**
* Normal 5.0 V undervoltage detection threshold (VCCA_UV_5)
*/
#define FS65_W_FS_VCCA_5D_NORMAL (0x00U << FS65_W_FS_VCCA_5D_SHIFT)
/**
* Degraded mode, lower undervoltage detection threshold applied (VCCA_UV_D)
*/
#define FS65_W_FS_VCCA_5D_DEGRADED (0x01U << FS65_W_FS_VCCA_5D_SHIFT)
/**
* Normal 5.0 V undervoltage detection threshold (VCORE_FB_UV)
*/
#define FS65_W_FS_VCORE_5D_NORMAL (0x00U << FS65_W_FS_VCORE_5D_SHIFT)
/**
* Degraded mode, lower undervoltage detection threshold applied (VCORE_FB_UV_D)
*/
#define FS65_W_FS_VCORE_5D_DEGRADED (0x01U << FS65_W_FS_VCORE_5D_SHIFT)
/******************************************************************************/
/* INIT_FAULT - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_FAULT_ADDR 0x24U
#define FS65_FS_INIT_FAULT_DEFAULT 0x05U
/**
* Configure RSTB and FS0B behavior when fault error counter >= intermediate value
*/
#define FS65_R_FS_FLT_ERR_IMP_MASK 0x03U
/**
* Configure CAN behavior when FS1B is asserted low
*/
#define FS65_R_FS_FS1B_CAN_IMPACT_MASK 0x04U
/**
* Configure the values of the fault error counter
*/
#define FS65_R_FS_FLT_ERR_FS_MASK 0x08U
/**
* Configure RSTB and FS0B behavior when fault error counter >= intermediate value
*/
#define FS65_W_FS_FLT_ERR_IMP_MASK 0x30U
/**
* Configure CAN behavior when FS1B is asserted low
*/
#define FS65_W_FS_FS1B_CAN_IMPACT_MASK 0x40U
/**
* Configure the values of the fault error counter
*/
#define FS65_W_FS_FLT_ERR_FS_MASK 0x80U
/**
* Configure RSTB and FS0B behavior when fault error counter >= intermediate value
*/
#define FS65_R_FS_FLT_ERR_IMP_SHIFT 0x00U
/**
* Configure CAN behavior when FS1B is asserted low
*/
#define FS65_R_FS_FS1B_CAN_IMPACT_SHIFT 0x02U
/**
* Configure the values of the fault error counter
*/
#define FS65_R_FS_FLT_ERR_FS_SHIFT 0x03U
/**
* Configure RSTB and FS0B behavior when fault error counter >= intermediate value
*/
#define FS65_W_FS_FLT_ERR_IMP_SHIFT 0x04U
/**
* Configure CAN behavior when FS1B is asserted low
*/
#define FS65_W_FS_FS1B_CAN_IMPACT_SHIFT 0x06U
/**
* Configure the values of the fault error counter
*/
#define FS65_W_FS_FLT_ERR_FS_SHIFT 0x07U
/**
* No effect on RSTB and FS0B
*/
#define FS65_R_FS_FLT_ERR_IMP_NO_EFFECT (0x00U << FS65_R_FS_FLT_ERR_IMP_SHIFT)
/**
* FS0B is asserted low if FLT_ERR_CNT >= intermediate value
*/
#define FS65_R_FS_FLT_ERR_IMP_FS0B (0x01U << FS65_R_FS_FLT_ERR_IMP_SHIFT)
/**
* RSTB is asserted low if FLT_ERR_CNT >= intermediate value and WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_R_FS_FLT_ERR_IMP_RSTB (0x02U << FS65_R_FS_FLT_ERR_IMP_SHIFT)
/**
* FS0B is asserted low if FLT_ERR_CNT >= intermediate value RSTB is asserted low if FLT_ERR_CNT >= intermediate value
* and WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_R_FS_FLT_ERR_IMP_FS0B_RSTB (0x03U << FS65_R_FS_FLT_ERR_IMP_SHIFT)
/**
* No effect
*/
#define FS65_R_FS_FS1B_CAN_IMPACT_NO_EFFECT (0x00U << FS65_R_FS_FS1B_CAN_IMPACT_SHIFT)
/**
* CAN in Rx only or sleep mode when FS1B is asserted (depends on CAN_DIS_CFG bit in INIT_WU2 register)
*/
#define FS65_R_FS_FS1B_CAN_IMPACT_RX_ONLY (0x01U << FS65_R_FS_FS1B_CAN_IMPACT_SHIFT)
/**
* intermediate = 3; final = 6
*/
#define FS65_R_FS_FLT_ERR_FS_INT3_FIN6 (0x00U << FS65_R_FS_FLT_ERR_FS_SHIFT)
/**
* intermediate = 1; final = 2
*/
#define FS65_R_FS_FLT_ERR_FS_INT1_FIN2 (0x01U << FS65_R_FS_FLT_ERR_FS_SHIFT)
/**
* No effect on RSTB and FS0B
*/
#define FS65_W_FS_FLT_ERR_IMP_NO_EFFECT (0x00U << FS65_W_FS_FLT_ERR_IMP_SHIFT)
/**
* FS0B is asserted low if FLT_ERR_CNT >= intermediate value
*/
#define FS65_W_FS_FLT_ERR_IMP_FS0B (0x01U << FS65_W_FS_FLT_ERR_IMP_SHIFT)
/**
* RSTB is asserted low if FLT_ERR_CNT >= intermediate value and WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_W_FS_FLT_ERR_IMP_RSTB (0x02U << FS65_W_FS_FLT_ERR_IMP_SHIFT)
/**
* FS0B is asserted low if FLT_ERR_CNT >= intermediate value RSTB is asserted low if FLT_ERR_CNT >= intermediate value
* and WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_W_FS_FLT_ERR_IMP_FS0B_RSTB (0x03U << FS65_W_FS_FLT_ERR_IMP_SHIFT)
/**
* No effect
*/
#define FS65_W_FS_FS1B_CAN_IMPACT_NO_EFFECT (0x00U << FS65_W_FS_FS1B_CAN_IMPACT_SHIFT)
/**
* CAN in Rx only or sleep mode when FS1B is asserted (depends on CAN_DIS_CFG bit in INIT_WU2 register)
*/
#define FS65_W_FS_FS1B_CAN_IMPACT_RX_ONLY (0x01U << FS65_W_FS_FS1B_CAN_IMPACT_SHIFT)
/**
* intermediate = 3; final = 6
*/
#define FS65_W_FS_FLT_ERR_FS_INT3_FIN6 (0x00U << FS65_W_FS_FLT_ERR_FS_SHIFT)
/**
* intermediate = 1; final = 2
*/
#define FS65_W_FS_FLT_ERR_FS_INT1_FIN2 (0x01U << FS65_W_FS_FLT_ERR_FS_SHIFT)
/******************************************************************************/
/* INIT_FSSM - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_FSSM_ADDR 0x25U
#define FS65_FS_INIT_FSSM_DEFAULT 0x04U
/**
* Configure the RSTB low duration time
*/
#define FS65_R_FS_RSTB_DURATION_MASK 0x01U
/**
* Configure the FCCU polarity
*/
#define FS65_R_FS_PS_MASK 0x02U
/**
* Configure the couple of IO_3:2 as safety inputs for FCCU monitoring
*/
#define FS65_R_FS_IO_23_FS_MASK 0x04U
/**
* Configure the couple of IO_4:5 as safety inputs for external IC error monitoring
*/
#define FS65_R_FS_IO_45_FS_MASK 0x08U
/**
* Configure the RSTB low duration time
*/
#define FS65_W_FS_RSTB_DURATION_MASK 0x10U
/**
* Configure the FCCU polarity
*/
#define FS65_W_FS_PS_MASK 0x20U
/**
* Configure the couple of IO_3:2 as safety inputs for FCCU monitoring
*/
#define FS65_W_FS_IO_23_FS_MASK 0x40U
/**
* Configure the couple of IO_4:5 as safety inputs for external IC error monitoring
*/
#define FS65_W_FS_IO_45_FS_MASK 0x80U
/**
* Configure the RSTB low duration time
*/
#define FS65_R_FS_RSTB_DURATION_SHIFT 0x00U
/**
* Configure the FCCU polarity
*/
#define FS65_R_FS_PS_SHIFT 0x01U
/**
* Configure the couple of IO_3:2 as safety inputs for FCCU monitoring
*/
#define FS65_R_FS_IO_23_FS_SHIFT 0x02U
/**
* Configure the couple of IO_4:5 as safety inputs for external IC error monitoring
*/
#define FS65_R_FS_IO_45_FS_SHIFT 0x03U
/**
* Configure the RSTB low duration time
*/
#define FS65_W_FS_RSTB_DURATION_SHIFT 0x04U
/**
* Configure the FCCU polarity
*/
#define FS65_W_FS_PS_SHIFT 0x05U
/**
* Configure the couple of IO_3:2 as safety inputs for FCCU monitoring
*/
#define FS65_W_FS_IO_23_FS_SHIFT 0x06U
/**
* Configure the couple of IO_4:5 as safety inputs for external IC error monitoring
*/
#define FS65_W_FS_IO_45_FS_SHIFT 0x07U
/**
* 10 ms
*/
#define FS65_R_FS_RSTB_DURATION_10MS (0x00U << FS65_R_FS_RSTB_DURATION_SHIFT)
/**
* 1.0 ms
*/
#define FS65_R_FS_RSTB_DURATION_1MS (0x01U << FS65_R_FS_RSTB_DURATION_SHIFT)
/**
* Fccu_eaout_1:0 active high
*/
#define FS65_R_FS_PS_HIGH (0x00U << FS65_R_FS_PS_SHIFT)
/**
* Fccu_eaout_1:0 active low
*/
#define FS65_R_FS_PS_LOW (0x01U << FS65_R_FS_PS_SHIFT)
/**
* Not_safety
*/
#define FS65_R_FS_IO_23_FS_NOT_SAFETY (0x00U << FS65_R_FS_IO_23_FS_SHIFT)
/**
* Safety_critical
*/
#define FS65_R_FS_IO_23_FS_SAFETY_CRITICAL (0x01U << FS65_R_FS_IO_23_FS_SHIFT)
/**
* Not safety
*/
#define FS65_R_FS_IO_45_FS_NOT_SAFETY (0x00U << FS65_R_FS_IO_45_FS_SHIFT)
/**
* Safety critical
*/
#define FS65_R_FS_IO_45_FS_SAFETY_CRITICAL (0x01U << FS65_R_FS_IO_45_FS_SHIFT)
/**
* 10 ms
*/
#define FS65_W_FS_RSTB_DURATION_10MS (0x00U << FS65_W_FS_RSTB_DURATION_SHIFT)
/**
* 1.0 ms
*/
#define FS65_W_FS_RSTB_DURATION_1MS (0x01U << FS65_W_FS_RSTB_DURATION_SHIFT)
/**
* Fccu_eaout_1:0 active high
*/
#define FS65_W_FS_PS_HIGH (0x00U << FS65_W_FS_PS_SHIFT)
/**
* Fccu_eaout_1:0 active low
*/
#define FS65_W_FS_PS_LOW (0x01U << FS65_W_FS_PS_SHIFT)
/**
* Not_safety
*/
#define FS65_W_FS_IO_23_FS_NOT_SAFETY (0x00U << FS65_W_FS_IO_23_FS_SHIFT)
/**
* Safety_critical
*/
#define FS65_W_FS_IO_23_FS_SAFETY_CRITICAL (0x01U << FS65_W_FS_IO_23_FS_SHIFT)
/**
* Not safety
*/
#define FS65_W_FS_IO_45_FS_NOT_SAFETY (0x00U << FS65_W_FS_IO_45_FS_SHIFT)
/**
* Safety critical
*/
#define FS65_W_FS_IO_45_FS_SAFETY_CRITICAL (0x01U << FS65_W_FS_IO_45_FS_SHIFT)
/******************************************************************************/
/* INIT_SF_IMPACT - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_SF_IMPACT_ADDR 0x26U
#define FS65_FS_INIT_SF_IMPACT_DEFAULT 0x01U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_R_FS_WD_IMPACT_MASK 0x03U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_R_FS_DIS_8S_MASK 0x04U
/**
* FS1B delay or FS1B duration mode selection
*/
#define FS65_R_FS_TDLY_TDUR_MASK 0x08U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_W_FS_WD_IMPACT_MASK 0x30U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_W_FS_DIS_8S_MASK 0x40U
/**
* FS1B delay or FS1B duration mode selection
*/
#define FS65_W_FS_TDLY_TDUR_MASK 0x80U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_R_FS_WD_IMPACT_SHIFT 0x00U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_R_FS_DIS_8S_SHIFT 0x02U
/**
* FS1B delay or FS1B duration mode selection
*/
#define FS65_R_FS_TDLY_TDUR_SHIFT 0x03U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_W_FS_WD_IMPACT_SHIFT 0x04U
/**
* Watchdog impact on RSTB and/or FS0B assertion
*/
#define FS65_W_FS_DIS_8S_SHIFT 0x06U
/**
* FS1B delay or FS1B duration mode selection
*/
#define FS65_W_FS_TDLY_TDUR_SHIFT 0x07U
/**
* No effect on RSTB and FS0B if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_R_FS_WD_IMPACT_NO_EFFECT (0x00U << FS65_R_FS_WD_IMPACT_SHIFT)
/**
* RSTB only is asserted low if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_R_FS_WD_IMPACT_RSTB (0x01U << FS65_R_FS_WD_IMPACT_SHIFT)
/**
* FS0B only is asserted low if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_R_FS_WD_IMPACT_FS0B (0x02U << FS65_R_FS_WD_IMPACT_SHIFT)
/**
* RSTB and FS0B are asserted low if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_R_FS_WD_IMPACT_RSTB_FS0B (0x03U << FS65_R_FS_WD_IMPACT_SHIFT)
/**
* Enabled
*/
#define FS65_R_FS_DIS_8S_ENABLED (0x00U << FS65_R_FS_DIS_8S_SHIFT)
/**
* Disabled
*/
#define FS65_R_FS_DIS_8S_DISABLED (0x01U << FS65_R_FS_DIS_8S_SHIFT)
/**
* FS1B tDELAY mode
*/
#define FS65_R_FS_TDLY_TDUR_DELAY (0x00U << FS65_R_FS_TDLY_TDUR_SHIFT)
/**
* FS1B tDURATION mode
*/
#define FS65_R_FS_TDLY_TDUR_DURATION (0x01U << FS65_R_FS_TDLY_TDUR_SHIFT)
/**
* No effect on RSTB and FS0B if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_W_FS_WD_IMPACT_NO_EFFECT (0x00U << FS65_W_FS_WD_IMPACT_SHIFT)
/**
* RSTB only is asserted low if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_W_FS_WD_IMPACT_RSTB (0x01U << FS65_W_FS_WD_IMPACT_SHIFT)
/**
* FS0B only is asserted low if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_W_FS_WD_IMPACT_FS0B (0x02U << FS65_W_FS_WD_IMPACT_SHIFT)
/**
* RSTB and FS0B are asserted low if WD error counter = WD_CNT_ERR[1:0]
*/
#define FS65_W_FS_WD_IMPACT_RSTB_FS0B (0x03U << FS65_W_FS_WD_IMPACT_SHIFT)
/**
* Enabled
*/
#define FS65_W_FS_DIS_8S_ENABLED (0x00U << FS65_W_FS_DIS_8S_SHIFT)
/**
* Disabled
*/
#define FS65_W_FS_DIS_8S_DISABLED (0x01U << FS65_W_FS_DIS_8S_SHIFT)
/**
* FS1B tDELAY mode
*/
#define FS65_W_FS_TDLY_TDUR_DELAY (0x00U << FS65_W_FS_TDLY_TDUR_SHIFT)
/**
* FS1B tDURATION mode
*/
#define FS65_W_FS_TDLY_TDUR_DURATION (0x01U << FS65_W_FS_TDLY_TDUR_SHIFT)
/******************************************************************************/
/* WD_WINDOW - Type: RW */
/******************************************************************************/
#define FS65_FS_WD_WINDOW_ADDR 0x27U
#define FS65_FS_WD_WINDOW_DEFAULT 0x03U
/**
* Configure the watchdog window duration. Duty cycle if set to 50 %
*/
#define FS65_R_FS_WD_WINDOW_MASK 0x0FU
/**
* Configure the watchdog window duration. Duty cycle if set to 50 %
*/
#define FS65_W_FS_WD_WINDOW_MASK 0xF0U
/**
* Configure the watchdog window duration. Duty cycle if set to 50 %
*/
#define FS65_R_FS_WD_WINDOW_SHIFT 0x00U
/**
* Configure the watchdog window duration. Duty cycle if set to 50 %
*/
#define FS65_W_FS_WD_WINDOW_SHIFT 0x04U
/**
* Disable (in INIT phase only)
*/
#define FS65_R_FS_WD_WINDOW_DISABLE (0x00U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 1.0 ms
*/
#define FS65_R_FS_WD_WINDOW_1MS (0x01U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 2.0 ms
*/
#define FS65_R_FS_WD_WINDOW_2MS (0x02U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 3.0 ms
*/
#define FS65_R_FS_WD_WINDOW_3MS (0x03U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 4.0 ms
*/
#define FS65_R_FS_WD_WINDOW_4MS (0x04U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 6.0 ms
*/
#define FS65_R_FS_WD_WINDOW_6MS (0x05U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 8.0 ms
*/
#define FS65_R_FS_WD_WINDOW_8MS (0x06U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 12.0 ms
*/
#define FS65_R_FS_WD_WINDOW_12MS (0x07U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 16 ms
*/
#define FS65_R_FS_WD_WINDOW_16MS (0x08U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 24 ms
*/
#define FS65_R_FS_WD_WINDOW_24MS (0x09U << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 32 ms
*/
#define FS65_R_FS_WD_WINDOW_32MS (0x0AU << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 64 ms
*/
#define FS65_R_FS_WD_WINDOW_64MS (0x0BU << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 128 ms
*/
#define FS65_R_FS_WD_WINDOW_128MS (0x0CU << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 256 ms
*/
#define FS65_R_FS_WD_WINDOW_256MS (0x0DU << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 512 ms
*/
#define FS65_R_FS_WD_WINDOW_512MS (0x0EU << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* 1024 ms
*/
#define FS65_R_FS_WD_WINDOW_1024MS (0x0FU << FS65_R_FS_WD_WINDOW_SHIFT)
/**
* Disable (in INIT phase only)
*/
#define FS65_W_FS_WD_WINDOW_DISABLE (0x00U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 1.0 ms
*/
#define FS65_W_FS_WD_WINDOW_1MS (0x01U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 2.0 ms
*/
#define FS65_W_FS_WD_WINDOW_2MS (0x02U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 3.0 ms
*/
#define FS65_W_FS_WD_WINDOW_3MS (0x03U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 4.0 ms
*/
#define FS65_W_FS_WD_WINDOW_4MS (0x04U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 6.0 ms
*/
#define FS65_W_FS_WD_WINDOW_6MS (0x05U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 8.0 ms
*/
#define FS65_W_FS_WD_WINDOW_8MS (0x06U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 12.0 ms
*/
#define FS65_W_FS_WD_WINDOW_12MS (0x07U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 16 ms
*/
#define FS65_W_FS_WD_WINDOW_16MS (0x08U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 24 ms
*/
#define FS65_W_FS_WD_WINDOW_24MS (0x09U << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 32 ms
*/
#define FS65_W_FS_WD_WINDOW_32MS (0x0AU << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 64 ms
*/
#define FS65_W_FS_WD_WINDOW_64MS (0x0BU << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 128 ms
*/
#define FS65_W_FS_WD_WINDOW_128MS (0x0CU << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 256 ms
*/
#define FS65_W_FS_WD_WINDOW_256MS (0x0DU << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 512 ms
*/
#define FS65_W_FS_WD_WINDOW_512MS (0x0EU << FS65_W_FS_WD_WINDOW_SHIFT)
/**
* 1024 ms
*/
#define FS65_W_FS_WD_WINDOW_1024MS (0x0FU << FS65_W_FS_WD_WINDOW_SHIFT)
/******************************************************************************/
/* WD_LFSR - Type: RW */
/******************************************************************************/
#define FS65_FS_WD_LFSR_ADDR 0x28U
#define FS65_FS_WD_LFSR_DEFAULT 0xB2U
/**
* WD 8 bits LFSR value. Used to write the seed at any time. Default value at start-up or after a power on reset: 0xB2
* bit7:bit0: 10110010. Value Bit7:Bit0: 1111 1111 is prohibited. During a write command, MISO reports the previous
* register content.
*/
#define FS65_RW_FS_WD_LFSR_MASK 0xFFU
/**
* WD 8 bits LFSR value. Used to write the seed at any time. Default value at start-up or after a power on reset: 0xB2
* bit7:bit0: 10110010. Value Bit7:Bit0: 1111 1111 is prohibited. During a write command, MISO reports the previous
* register content.
*/
#define FS65_RW_FS_WD_LFSR_SHIFT 0x00U
/******************************************************************************/
/* INIT_WD_CNT - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_WD_CNT_ADDR 0x2CU
#define FS65_FS_INIT_WD_CNT_DEFAULT 0x00U
/**
* Configure the maximum value of the WD refresh counter
*/
#define FS65_R_FS_WD_CNT_RFR_MASK 0x03U
/**
* Configure the maximum value of the WD error counter
*/
#define FS65_R_FS_WD_CNT_ERR_MASK 0x0CU
/**
* Configure the maximum value of the WD refresh counter
*/
#define FS65_W_FS_WD_CNT_RFR_MASK 0x30U
/**
* Configure the maximum value of the WD error counter
*/
#define FS65_W_FS_WD_CNT_ERR_MASK 0xC0U
/**
* Configure the maximum value of the WD refresh counter
*/
#define FS65_R_FS_WD_CNT_RFR_SHIFT 0x00U
/**
* Configure the maximum value of the WD error counter
*/
#define FS65_R_FS_WD_CNT_ERR_SHIFT 0x02U
/**
* Configure the maximum value of the WD refresh counter
*/
#define FS65_W_FS_WD_CNT_RFR_SHIFT 0x04U
/**
* Configure the maximum value of the WD error counter
*/
#define FS65_W_FS_WD_CNT_ERR_SHIFT 0x06U
/**
* 6
*/
#define FS65_R_FS_WD_CNT_RFR_6 (0x00U << FS65_R_FS_WD_CNT_RFR_SHIFT)
/**
* 4
*/
#define FS65_R_FS_WD_CNT_RFR_4 (0x01U << FS65_R_FS_WD_CNT_RFR_SHIFT)
/**
* 2
*/
#define FS65_R_FS_WD_CNT_RFR_2 (0x02U << FS65_R_FS_WD_CNT_RFR_SHIFT)
/**
* 1
*/
#define FS65_R_FS_WD_CNT_RFR_1 (0x03U << FS65_R_FS_WD_CNT_RFR_SHIFT)
/**
* 6
*/
#define FS65_R_FS_WD_CNT_ERR_6 (0x00U << FS65_R_FS_WD_CNT_ERR_SHIFT)
/**
* 4
*/
#define FS65_R_FS_WD_CNT_ERR_4 (0x02U << FS65_R_FS_WD_CNT_ERR_SHIFT)
/**
* 2
*/
#define FS65_R_FS_WD_CNT_ERR_2 (0x03U << FS65_R_FS_WD_CNT_ERR_SHIFT)
/**
* 6
*/
#define FS65_W_FS_WD_CNT_RFR_6 (0x00U << FS65_W_FS_WD_CNT_RFR_SHIFT)
/**
* 4
*/
#define FS65_W_FS_WD_CNT_RFR_4 (0x01U << FS65_W_FS_WD_CNT_RFR_SHIFT)
/**
* 2
*/
#define FS65_W_FS_WD_CNT_RFR_2 (0x02U << FS65_W_FS_WD_CNT_RFR_SHIFT)
/**
* 1
*/
#define FS65_W_FS_WD_CNT_RFR_1 (0x03U << FS65_W_FS_WD_CNT_RFR_SHIFT)
/**
* 6
*/
#define FS65_W_FS_WD_CNT_ERR_6 (0x00U << FS65_W_FS_WD_CNT_ERR_SHIFT)
/**
* 4
*/
#define FS65_W_FS_WD_CNT_ERR_4 (0x02U << FS65_W_FS_WD_CNT_ERR_SHIFT)
/**
* 2
*/
#define FS65_W_FS_WD_CNT_ERR_2 (0x03U << FS65_W_FS_WD_CNT_ERR_SHIFT)
/******************************************************************************/
/* INIT_VCORE_OVUV_IMPACT - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_VCORE_OVUV_IMPACT_ADDR 0x31U
#define FS65_VCORE_OVUV_IMPACT_DEFAULT 0x0EU
/**
* VCORE_FB undervoltage safety impact
*/
#define FS65_R_FS_VCORE_FS_UV_MASK 0x03U
/**
* VCORE_FB overvoltage safety impact
*/
#define FS65_R_FS_VCORE_FS_OV_MASK 0x0CU
/**
* VCORE_FB undervoltage safety impact
*/
#define FS65_W_FS_VCORE_FS_UV_MASK 0x30U
/**
* VCORE_FB overvoltage safety impact
*/
#define FS65_W_FS_VCORE_FS_OV_MASK 0xC0U
/**
* VCORE_FB undervoltage safety impact
*/
#define FS65_R_FS_VCORE_FS_UV_SHIFT 0x00U
/**
* VCORE_FB overvoltage safety impact
*/
#define FS65_R_FS_VCORE_FS_OV_SHIFT 0x02U
/**
* VCORE_FB undervoltage safety impact
*/
#define FS65_W_FS_VCORE_FS_UV_SHIFT 0x04U
/**
* VCORE_FB overvoltage safety impact
*/
#define FS65_W_FS_VCORE_FS_OV_SHIFT 0x06U
/**
* No effect of VCORE_FB_UV on RSTB and FS0B
*/
#define FS65_R_FS_VCORE_FS_UV_NO_EFFECT (0x00U << FS65_R_FS_VCORE_FS_UV_SHIFT)
/**
* VCORE_FB_UV does have an impact on RSTB only
*/
#define FS65_R_FS_VCORE_FS_UV_RSTB (0x01U << FS65_R_FS_VCORE_FS_UV_SHIFT)
/**
* VCORE_FB_UV does have an impact on FS0B only
*/
#define FS65_R_FS_VCORE_FS_UV_FS0B (0x02U << FS65_R_FS_VCORE_FS_UV_SHIFT)
/**
* VCORE_FB_UV does have an impact on RSTB and FS0B
*/
#define FS65_R_FS_VCORE_FS_UV_RSTB_FS0B (0x03U << FS65_R_FS_VCORE_FS_UV_SHIFT)
/**
* No effect of VCORE_FB_OV on RSTB and FS0B
*/
#define FS65_R_FS_VCORE_FS_OV_NO_EFFECT (0x00U << FS65_R_FS_VCORE_FS_OV_SHIFT)
/**
* VCORE_FB_OV does have an impact on RSTB only
*/
#define FS65_R_FS_VCORE_FS_OV_RSTB (0x01U << FS65_R_FS_VCORE_FS_OV_SHIFT)
/**
* VCORE_FB_OV does have an impact on FS0B only
*/
#define FS65_R_FS_VCORE_FS_OV_FS0B (0x02U << FS65_R_FS_VCORE_FS_OV_SHIFT)
/**
* VCORE_FB_OV does have an impact on RSTB and FS0B
*/
#define FS65_R_FS_VCORE_FS_OV_RSTB_FS0B (0x03U << FS65_R_FS_VCORE_FS_OV_SHIFT)
/**
* No effect of VCORE_FB_UV on RSTB and FS0B
*/
#define FS65_W_FS_VCORE_FS_UV_NO_EFFECT (0x00U << FS65_W_FS_VCORE_FS_UV_SHIFT)
/**
* VCORE_FB_UV does have an impact on RSTB only
*/
#define FS65_W_FS_VCORE_FS_UV_RSTB (0x01U << FS65_W_FS_VCORE_FS_UV_SHIFT)
/**
* VCORE_FB_UV does have an impact on FS0B only
*/
#define FS65_W_FS_VCORE_FS_UV_FS0B (0x02U << FS65_W_FS_VCORE_FS_UV_SHIFT)
/**
* VCORE_FB_UV does have an impact on RSTB and FS0B
*/
#define FS65_W_FS_VCORE_FS_UV_RSTB_FS0B (0x03U << FS65_W_FS_VCORE_FS_UV_SHIFT)
/**
* No effect of VCORE_FB_OV on RSTB and FS0B
*/
#define FS65_W_FS_VCORE_FS_OV_NO_EFFECT (0x00U << FS65_W_FS_VCORE_FS_OV_SHIFT)
/**
* VCORE_FB_OV does have an impact on RSTB only
*/
#define FS65_W_FS_VCORE_FS_OV_RSTB (0x01U << FS65_W_FS_VCORE_FS_OV_SHIFT)
/**
* VCORE_FB_OV does have an impact on FS0B only
*/
#define FS65_W_FS_VCORE_FS_OV_FS0B (0x02U << FS65_W_FS_VCORE_FS_OV_SHIFT)
/**
* VCORE_FB_OV does have an impact on RSTB and FS0B
*/
#define FS65_W_FS_VCORE_FS_OV_RSTB_FS0B (0x03U << FS65_W_FS_VCORE_FS_OV_SHIFT)
/******************************************************************************/
/* INIT_VCCA_OVUV_IMPACT - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_VCCA_OVUV_IMPACT_ADDR 0x32U
#define FS65_FS_INIT_VCCA_OVUV_IMPACT_DEFAULT 0x0EU
/**
* VCCA undervoltage safety impact
*/
#define FS65_R_FS_VCCA_FS_UV_MASK 0x03U
/**
* VCCA overvoltage safety impact
*/
#define FS65_R_FS_VCCA_FS_OV_MASK 0x0CU
/**
* VCCA undervoltage safety impact
*/
#define FS65_W_FS_VCCA_FS_UV_MASK 0x30U
/**
* VCCA overvoltage safety impact
*/
#define FS65_W_FS_VCCA_FS_OV_MASK 0xC0U
/**
* VCCA undervoltage safety impact
*/
#define FS65_R_FS_VCCA_FS_UV_SHIFT 0x00U
/**
* VCCA overvoltage safety impact
*/
#define FS65_R_FS_VCCA_FS_OV_SHIFT 0x02U
/**
* VCCA undervoltage safety impact
*/
#define FS65_W_FS_VCCA_FS_UV_SHIFT 0x04U
/**
* VCCA overvoltage safety impact
*/
#define FS65_W_FS_VCCA_FS_OV_SHIFT 0x06U
/**
* No effect of VCCA_UV on RSTB and FS0B
*/
#define FS65_R_FS_VCCA_FS_UV_NO_EFFECT (0x00U << FS65_R_FS_VCCA_FS_UV_SHIFT)
/**
* VCCA_UV does have an impact on RSTB only
*/
#define FS65_R_FS_VCCA_FS_UV_RSTB (0x01U << FS65_R_FS_VCCA_FS_UV_SHIFT)
/**
* VCCA_UV does have an impact on FS0B only
*/
#define FS65_R_FS_VCCA_FS_UV_FS0B (0x02U << FS65_R_FS_VCCA_FS_UV_SHIFT)
/**
* VCCA_UV does have an impact on RSTB and FS0B
*/
#define FS65_R_FS_VCCA_FS_UV_RSTB_FS0B (0x03U << FS65_R_FS_VCCA_FS_UV_SHIFT)
/**
* No effect of VCCA_OV on RSTB and FS0B
*/
#define FS65_R_FS_VCCA_FS_OV_NO_EFFECT (0x00U << FS65_R_FS_VCCA_FS_OV_SHIFT)
/**
* VCCA_OV does have an impact on RSTB only
*/
#define FS65_R_FS_VCCA_FS_OV_RSTB (0x01U << FS65_R_FS_VCCA_FS_OV_SHIFT)
/**
* VCCA_OV does have an impact on FS0B only
*/
#define FS65_R_FS_VCCA_FS_OV_FS0B (0x02U << FS65_R_FS_VCCA_FS_OV_SHIFT)
/**
* VCCA_OV does have an impact on RSTB and FS0B
*/
#define FS65_R_FS_VCCA_FS_OV_RSTB_FS0B (0x03U << FS65_R_FS_VCCA_FS_OV_SHIFT)
/**
* No effect of VCCA_UV on RSTB and FS0B
*/
#define FS65_W_FS_VCCA_FS_UV_NO_EFFECT (0x00U << FS65_W_FS_VCCA_FS_UV_SHIFT)
/**
* VCCA_UV does have an impact on RSTB only
*/
#define FS65_W_FS_VCCA_FS_UV_RSTB (0x01U << FS65_W_FS_VCCA_FS_UV_SHIFT)
/**
* VCCA_UV does have an impact on FS0B only
*/
#define FS65_W_FS_VCCA_FS_UV_FS0B (0x02U << FS65_W_FS_VCCA_FS_UV_SHIFT)
/**
* VCCA_UV does have an impact on RSTB and FS0B
*/
#define FS65_W_FS_VCCA_FS_UV_RSTB_FS0B (0x03U << FS65_W_FS_VCCA_FS_UV_SHIFT)
/**
* No effect of VCCA_OV on RSTB and FS0B
*/
#define FS65_W_FS_VCCA_FS_OV_NO_EFFECT (0x00U << FS65_W_FS_VCCA_FS_OV_SHIFT)
/**
* VCCA_OV does have an impact on RSTB only
*/
#define FS65_W_FS_VCCA_FS_OV_RSTB (0x01U << FS65_W_FS_VCCA_FS_OV_SHIFT)
/**
* VCCA_OV does have an impact on FS0B only
*/
#define FS65_W_FS_VCCA_FS_OV_FS0B (0x02U << FS65_W_FS_VCCA_FS_OV_SHIFT)
/**
* VCCA_OV does have an impact on RSTB and FS0B
*/
#define FS65_W_FS_VCCA_FS_OV_RSTB_FS0B (0x03U << FS65_W_FS_VCCA_FS_OV_SHIFT)
/******************************************************************************/
/* INIT_VAUX_OVUV_IMPACT - Type: RW */
/******************************************************************************/
#define FS65_FS_INIT_VAUX_OVUV_IMPACT_ADDR 0x33U
#define FS65_FS_INIT_VAUX_OVUV_IMPACT_DEFAULT 0x0EU
/**
* VAUX undervoltage safety impact
*/
#define FS65_R_FS_VAUX_FS_UV_MASK 0x03U
/**
* VAUX overvoltage safety impact
*/
#define FS65_R_FS_VAUX_FS_OV_MASK 0x0CU
/**
* VAUX undervoltage safety impact
*/
#define FS65_W_FS_VAUX_FS_UV_MASK 0x30U
/**
* VAUX overvoltage safety impact
*/
#define FS65_W_FS_VAUX_FS_OV_MASK 0xC0U
/**
* VAUX undervoltage safety impact
*/
#define FS65_R_FS_VAUX_FS_UV_SHIFT 0x00U
/**
* VAUX overvoltage safety impact
*/
#define FS65_R_FS_VAUX_FS_OV_SHIFT 0x02U
/**
* VAUX undervoltage safety impact
*/
#define FS65_W_FS_VAUX_FS_UV_SHIFT 0x04U
/**
* VAUX overvoltage safety impact
*/
#define FS65_W_FS_VAUX_FS_OV_SHIFT 0x06U
/**
* No effect of VAUX_UV on RSTB and FS0B
*/
#define FS65_R_FS_VAUX_FS_UV_NO_EFFECT (0x00U << FS65_R_FS_VAUX_FS_UV_SHIFT)
/**
* VAUX_UV does have an impact on RSTB only
*/
#define FS65_R_FS_VAUX_FS_UV_RSTB (0x01U << FS65_R_FS_VAUX_FS_UV_SHIFT)
/**
* VAUX_UV does have an impact on FS0B only
*/
#define FS65_R_FS_VAUX_FS_UV_FS0B (0x02U << FS65_R_FS_VAUX_FS_UV_SHIFT)
/**
* VAUX_UV does have an impact on RSTB and FS0B
*/
#define FS65_R_FS_VAUX_FS_UV_RSTB_FS0B (0x03U << FS65_R_FS_VAUX_FS_UV_SHIFT)
/**
* No effect of VAUX_OV on RSTB and FS0B
*/
#define FS65_R_FS_VAUX_FS_OV_NO_EFFECT (0x00U << FS65_R_FS_VAUX_FS_OV_SHIFT)
/**
* VAUX_OV does have an impact on RSTB only
*/
#define FS65_R_FS_VAUX_FS_OV_RSTB (0x01U << FS65_R_FS_VAUX_FS_OV_SHIFT)
/**
* VAUX_OV does have an impact on FS0B only
*/
#define FS65_R_FS_VAUX_FS_OV_FS0B (0x02U << FS65_R_FS_VAUX_FS_OV_SHIFT)
/**
* VAUX_OV does have an impact on RSTB and FS0B
*/
#define FS65_R_FS_VAUX_FS_OV_RSTB_FS0B (0x03U << FS65_R_FS_VAUX_FS_OV_SHIFT)
/**
* No effect of VAUX_UV on RSTB and FS0B
*/
#define FS65_W_FS_VAUX_FS_UV_NO_EFFECT (0x00U << FS65_W_FS_VAUX_FS_UV_SHIFT)
/**
* VAUX_UV does have an impact on RSTB only
*/
#define FS65_W_FS_VAUX_FS_UV_RSTB (0x01U << FS65_W_FS_VAUX_FS_UV_SHIFT)
/**
* VAUX_UV does have an impact on FS0B only
*/
#define FS65_W_FS_VAUX_FS_UV_FS0B (0x02U << FS65_W_FS_VAUX_FS_UV_SHIFT)
/**
* VAUX_UV does have an impact on RSTB and FS0B
*/
#define FS65_W_FS_VAUX_FS_UV_RSTB_FS0B (0x03U << FS65_W_FS_VAUX_FS_UV_SHIFT)
/**
* No effect of VAUX_OV on RSTB and FS0B
*/
#define FS65_W_FS_VAUX_FS_OV_NO_EFFECT (0x00U << FS65_W_FS_VAUX_FS_OV_SHIFT)
/**
* VAUX_OV does have an impact on RSTB only
*/
#define FS65_W_FS_VAUX_FS_OV_RSTB (0x01U << FS65_W_FS_VAUX_FS_OV_SHIFT)
/**
* VAUX_OV does have an impact on FS0B only
*/
#define FS65_W_FS_VAUX_FS_OV_FS0B (0x02U << FS65_W_FS_VAUX_FS_OV_SHIFT)
/**
* VAUX_OV does have an impact on RSTB and FS0B
*/
#define FS65_W_FS_VAUX_FS_OV_RSTB_FS0B (0x03U << FS65_W_FS_VAUX_FS_OV_SHIFT)
/******************************************************************************/
/* INIT_INT - Type: RW */
/******************************************************************************/
#define FS65_M_INIT_INT_ADDR 0x04U
#define FS65_M_INIT_INT_DEFAULT 0x00U
/**
* Inhibit the interrupt for CAN error bits
*/
#define FS65_RW_M_INT_INH_CAN_MASK 0x01U
/**
* Inhibit the interrupt for VCCA/VAUX and VCAN status event
*/
#define FS65_RW_M_INT_INH_VOTHER_MASK 0x02U
/**
* Inhibit the interrupt for VCORE status event
*/
#define FS65_RW_M_INT_INH_VCORE_MASK 0x04U
/**
* Inhibit the interrupt for VPRE status event
*/
#define FS65_RW_M_INT_INH_VPRE_MASK 0x08U
/**
* Inhibit the interrupt for VSNS_UV
*/
#define FS65_RW_M_INT_INH_VSNS_MASK 0x10U
/**
* Inhibit ALL the interrupt
*/
#define FS65_RW_M_INT_INH_ALL_MASK 0x20U
/**
* Inhibit the interrupt for LIN error bits
*/
#define FS65_RW_M_INT_INH_LIN_MASK 0x40U
/**
* Define the duration of the interrupt pulse
*/
#define FS65_RW_M_NT_DURATION_MASK 0x80U
/**
* Inhibit the interrupt for CAN error bits
*/
#define FS65_RW_M_INT_INH_CAN_SHIFT 0x00U
/**
* Inhibit the interrupt for VCCA/VAUX and VCAN status event
*/
#define FS65_RW_M_INT_INH_VOTHER_SHIFT 0x01U
/**
* Inhibit the interrupt for VCORE status event
*/
#define FS65_RW_M_INT_INH_VCORE_SHIFT 0x02U
/**
* Inhibit the interrupt for VPRE status event
*/
#define FS65_RW_M_INT_INH_VPRE_SHIFT 0x03U
/**
* Inhibit the interrupt for VSNS_UV
*/
#define FS65_RW_M_INT_INH_VSNS_SHIFT 0x04U
/**
* Inhibit ALL the interrupt
*/
#define FS65_RW_M_INT_INH_ALL_SHIFT 0x05U
/**
* Inhibit the interrupt for LIN error bits
*/
#define FS65_RW_M_INT_INH_LIN_SHIFT 0x06U
/**
* Define the duration of the interrupt pulse
*/
#define FS65_RW_M_NT_DURATION_SHIFT 0x07U
/**
* All INT sources
*/
#define FS65_RW_M_INT_INH_CAN_ALL_SOURCES (0x00U << FS65_RW_M_INT_INH_CAN_SHIFT)
/**
* CAN error bits change inhibited
*/
#define FS65_RW_M_INT_INH_CAN_CAN_INHIBITED (0x01U << FS65_RW_M_INT_INH_CAN_SHIFT)
/**
* All INT sources
*/
#define FS65_RW_M_INT_INH_VOTHER_ALL_SOURCES (0x00U << FS65_RW_M_INT_INH_VOTHER_SHIFT)
/**
* VCCA/VAUX/VCAN status change inhibited
*/
#define FS65_RW_M_INT_INH_VOTHER_VOTHER_INHIBITED (0x01U << FS65_RW_M_INT_INH_VOTHER_SHIFT)
/**
* All INT sources
*/
#define FS65_RW_M_INT_INH_VCORE_ALL_SOURCES (0x00U << FS65_RW_M_INT_INH_VCORE_SHIFT)
/**
* VCORE status change inhibited
*/
#define FS65_RW_M_INT_INH_VCORE_VCORE_INHIBITED (0x01U << FS65_RW_M_INT_INH_VCORE_SHIFT)
/**
* All INT sources
*/
#define FS65_RW_M_INT_INH_VPRE_ALL_SOURCES (0x00U << FS65_RW_M_INT_INH_VPRE_SHIFT)
/**
* VPRE status change inhibited
*/
#define FS65_RW_M_INT_INH_VPRE_VPRE_INHIBITED (0x01U << FS65_RW_M_INT_INH_VPRE_SHIFT)
/**
* All INT sources
*/
#define FS65_RW_M_INT_INH_VSNS_ALL_SOURCES (0x00U << FS65_RW_M_INT_INH_VSNS_SHIFT)
/**
* VSNS_UV INT inhibited
*/
#define FS65_RW_M_INT_INH_VSNS_VSNS_UV_INHIBITED (0x01U << FS65_RW_M_INT_INH_VSNS_SHIFT)
/**
* All INT sources
*/
#define FS65_RW_M_INT_INH_ALL_ALL_SOURCES (0x00U << FS65_RW_M_INT_INH_ALL_SHIFT)
/**
* All INT inhibited
*/
#define FS65_RW_M_INT_INH_ALL_ALL_INHIBITED (0x01U << FS65_RW_M_INT_INH_ALL_SHIFT)
/**
* All INT sources
*/
#define FS65_RW_M_INT_INH_LIN_ALL_SOURCES (0x00U << FS65_RW_M_INT_INH_LIN_SHIFT)
/**
* LIN error bits change INHIBITED
*/
#define FS65_RW_M_INT_INH_LIN_LIN_INHIBITED (0x01U << FS65_RW_M_INT_INH_LIN_SHIFT)
/**
* 100 us
*/
#define FS65_RW_M_NT_DURATION_100US (0x00U << FS65_RW_M_NT_DURATION_SHIFT)
/**
* 25 us
*/
#define FS65_RW_M_NT_DURATION_25US (0x01U << FS65_RW_M_NT_DURATION_SHIFT)
#endif /* SBC_FS65_MAP_H__ */
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