FPGA 信号发生器

1锯齿波

module juchi
(
input clk,
input rst_n,
input [11:0]adr,
output reg  [9:0]q
);

always@(posedge clk or negedge rst_n)
	if(!rst_n) q<=0;
		else 
			q<=adr[11:2];
			
endmodule 

2.三角波

module sanjiao(
input OutClock,
input Reset,  
output reg [9:0] Q,
input   [11:0]Address 
);

always@(negedge OutClock or negedge Reset) 
 if(!Reset)    Q<=0;  
	 else if(Address >=2047)Q<=1024-Address [11:2];
          else Q<=Address [11:2];
endmodule 

3.方波

module fang
(
input clk,
input rst_n,
input [11:0]pwm,
input [11:0]adr,
output  reg [9:0]q
);
always@(posedge clk or negedge rst_n)
begin 
 if(!rst_n)q<=0;
	 else if(adr>=pwm)q<=512;
		  else q<=1024;
end 
endmodule