1:差分时钟 产生
差分时钟就是相位相反的两个时钟。只要在testbench初始化两个时钟,周期一样,初始值不一样就可以了
initial
begin
ref_clk_p = 1'b0;
ref_clk_n = 1'b1;
end
always
begin
# 20
ref_clk_p = ~ref_clk_p;
end
always
begin
# 20
ref_clk_n = ~ref_clk_n;
end
1:移相时钟产生
`timescale 1 ns / 1 ns
module tb;
reg absolute_clock;
wire derived_clock;
always
begin
# 5 absolute_clock = 0;
# 5 absolute_clock = 1;
end
assign # 2 derived_clock = absolute_clock;
endmodule
reg refclock;
reg vcoclock;
//assign vcoclock = 1'b0;
initial
begin
vcoclock = 1'b0;
refclock = 1'b0;
//refclock <= 1'b0;
//#5
//refclock <= 1'b1;
//#1
//vcoclock <= 1'b0;
//# 4
//refclock <= 1'b1;
end
always
begin
# 3 refclock = 0;
# 2 vcoclock = refclock;
# 3 refclock = 1;
# 2 vcoclock = refclock;
end
/*******************************************************
时钟信号的编写
*******************************************************/
'timescale 1ns/1ps //定义 时间单位/时间精度
/******************占空比50%(采用initial)**************/
parameter TIME_PERIOD = 10;
reg clock;
initial
begin
clock = 0;//初始化clock为0
forever
# (TIME_PERIOD/2) clock = ~clock;
end
/******************占空比50%(采用always)***************/
parameter TIME_PERIOD = 10;
reg clock;
initial
clock = 0;//初始化clock为0
always
# (TIME_PERIOD/2) clock = ~clock;
/******************非50%占空比(采用always)*************/
parameter HI_TIME = 5,
LO_TIME = 10;
reg clock;
always
begin
# HI_TIME clock = 0;
# LO_TIME clock = 1;
end
/***********固定数目时钟占空比50%(采用initial)*********/
parameter PULSE_COUNT = 4,
TIME_PERIOD = 10;
reg clock;
initial
begin
clock = 0;//初始化clock为0
repeat (2*PULSE_COUNT)
# (TIME_PERIOD/2) clock = ~clock;
end
/****************相移时钟信号(采用always)**************/
parameter HI_TIME = 5,
LO_TIME = 10,
PHASE_SHIFT = 2;
reg absolute_clock;
wire derived_clock;
always
begin
# HI_TIME absolute_clock = 0;
# LO_TIME absolute_clock = 1;
end
assign # PHASE_SHIFT derived_clock = absolute_clock;