一、原理介绍
状态机:一个状态机对应多种状态,每个状态由一个触发条件改变;
项目例子介绍:当检测到测试数据中“FPGA”四个字母连续出现,led状态改变;
二、实验代码
//项目文件
module FiniteStateMachine(clk,Rst_n,data,led);//检测FPGA
input clk;
input Rst_n;
input [7:0]data;//输入的数据
output reg led;
localparam
status_F = 4'b0001,
status_P = 4'b0010,
status_G = 4'b0100,
status_A = 4'b1000;
reg [3:0]check_status;
always@(posedge clk or negedge Rst_n)
if(!Rst_n)
begin
led <= 1'b1;
check_status = status_F;
end
else begin
case(check_status)
status_F:
if(check_status <= status_F)
check_status <= status_P;
else
check_status <= status_F;
status_P:
if(check_status <= status_P)
check_status <= status_G;
else
check_status <= status_F;
status_G:
if(check_status <= status_G)
check_status <= status_A;
else
check_status <= status_F;
status_A:
begin
check_status <= status_F;
if(data == "A")
led <= ~led;
else
led <= led;
end
default:check_status <= status_F;
endcase
end
endmodule
//测试文件
`timescale 1ns/1ns
`define timeperiod 20
module FiniteStateMachine_tb;
reg clk;
reg Rst_n;
reg [7:0]ASCII;
wire led;
FiniteStateMachine check0 (
.clk(clk),
.Rst_n(Rst_n),
.data(ASCII),
.led(led)
);
initial clk = 1;
always #(`timeperiod / 2) clk = ~clk;
initial begin
Rst_n = 0;
ASCII = 0;
#(`timeperiod*200);
Rst_n = 1;
#(`timeperiod*200);
forever begin
ASCII = "H";
#(`timeperiod);
ASCII = "e";
#(`timeperiod);
ASCII = "l";
#(`timeperiod);
ASCII = "l";
#(`timeperiod);
ASCII = "o";
#(`timeperiod);
ASCII = "F";
#(`timeperiod);
ASCII = "P";
#(`timeperiod);
ASCII = "G";
#(`timeperiod);
ASCII = "A";
#(`timeperiod);
ASCII = "H";
#(`timeperiod);
ASCII = "e";
#(`timeperiod);
ASCII = "l";
#(`timeperiod);
ASCII = "l";
#(`timeperiod);
ASCII = "o";
#(`timeperiod);
ASCII = "F";
#(`timeperiod);
ASCII = "P";
#(`timeperiod);
ASCII = "G";
#(`timeperiod);
ASCII = "A";
#(`timeperiod);
end
end
endmodule
三、项目总结
1、语法总结:
localparam:用于状态机参数定义;定义状态的先后。
2、注意点:在always块语句中,注意对变量进行初始化;