基于FPGA的图像卷积运算（支持多通道，多分辨率）

`timescale 1 ps / 1 ps
module tst_tb;

reg  clk ;
reg   rst_n ;

initial 
begin
    clk = 0 ;
    rst_n = 0;
    #100 rst_n =1 ;
end

    
always #5 clk <= ~clk ;

///----------------------------------------------------------------
reg  [7:0] data_buf [0:3071] ;
reg  [7:0] data_buf1 [0:8];
reg  [7:0] data_buf2 [0:8];
//path_d = 'E:/MATLAB/file/lei/data_input/dat_in.txt'
initial
begin
    //$readmemb()
    $readmemh ("E:/MATLAB/file/lei/data_input/dat_in32.txt", data_buf) ;
    $readmemh ("E:/MATLAB/file/lei/data_input/dat3_3_in.txt", data_buf1) ;
    $readmemh ("E:/MATLAB/file/lei/data_input/dat_biao.txt", data_buf2) ;
end 

parameter WIDTH=10'd32-1;
parameter WIDTH1=10'd32;
parameter CH_NUM=10'd3;
parameter M=12'd1024;

 

reg [7:0] data_2 ;
reg [3:0] cnt_2 ;
always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt_2 <= 0 ;
else if(cnt_2 == 4'd8)
        cnt_2 <= 4'd0 ;
else 
    cnt_2 <= cnt_2 + 1 ;
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    data_2 <= 0 ;
else
    data_2 <= data_buf2[cnt_2] ;
end

reg cnt_vs2;

reg [7:0]  data_i1 ;
reg [7:0] cnt_d1 ;
reg [7:0] data_3;
reg [7:0] data_4;
reg [7:0] data_5;
always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
 begin
    cnt_d1 <= 0 ;
    data_3 <= 0 ;
    data_4 <= 0 ;
    data_5 <= 0 ;
 end
else
 begin
    cnt_d1 <= data_2;
    data_3 <= cnt_d1;
    data_4 <= data_3;
    data_5 <= data_4;
 end
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    data_i1 <= 0 ;
else //if(cnt_vs2)
    data_i1 <= data_buf1[data_5] ;
end

 

reg [9:0] cnt_row;
reg [9:0] cnt_row1;
reg [9:0] cnt_col;
reg [9:0] cnt_col1;
reg [9:0] CH_NO;
reg [9:0] CH_NO1;

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt_vs2 <= 0 ;
else if(cnt_row1 == WIDTH1) 
        cnt_vs2 <= 0 ;
else
        cnt_vs2 <= 1'b1 ;
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt_row1 <= 0 ;
else if((cnt_row1 == WIDTH1)&&(CH_NO1 ==CH_NUM-1)&&(cnt_col1==WIDTH)&&(cnt_2==4'd8)) 
        cnt_row1 <= WIDTH1 ;
else if((CH_NO1 ==CH_NUM-1)&&(cnt_col1==WIDTH)&&(cnt_2==4'd8))
    cnt_row1 <= cnt_row1 + 1 ;
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt_col1 <= 0 ;
else if((cnt_col1==WIDTH)&&(cnt_2==4'd8)) 
        cnt_col1 <= 0 ;
else if(cnt_2==4'd8)
    cnt_col1 <= cnt_col1 + 1 ;
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    CH_NO1 <= 0 ;
else if((CH_NO1 ==CH_NUM-1)&&(cnt_col1==WIDTH)&&(cnt_2==4'd8)) 
        CH_NO1 <= 0 ;
else if((cnt_col1==WIDTH)&&(cnt_2==4'd8))
    CH_NO1 <= CH_NO1 + 1 ;
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt_row <= 0 ;
else
        cnt_row <= cnt_row1 ;
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt_col <= 0 ;
else
        cnt_col <= cnt_col1 ;
end

always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    CH_NO <= 0 ;
else
        CH_NO <= CH_NO1 ;
end

reg [9:0]cnt_row_sub1;
reg [9:0]cnt_row_add1;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
    begin
        cnt_row_sub1<=0;
    cnt_row_add1<=0;
    end    
    else
    begin
        cnt_row_sub1<=cnt_row-1;
    cnt_row_add1<=cnt_row+1;
    end
end

reg [9:0]cnt_row_delay;
reg [9:0]cnt_row_delay2;
reg [9:0]cnt_row_delay1;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
    begin
     cnt_row_delay<=0;
     cnt_row_delay2<=0;
     cnt_row_delay1<=0;
    end
    else
    begin
     cnt_row_delay<=cnt_row;
     cnt_row_delay2<=cnt_row_delay;
     cnt_row_delay1<=cnt_row_delay2;
    end
end

 

reg [9:0]WI_CH;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
      WI_CH<=0;
    else
      WI_CH<=WIDTH1*CH_NUM;
end

reg [23:0]row_offsets;
reg [23:0]row_offsets_sub1;
reg [23:0]row_offsets_add1;

always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
    begin
        row_offsets<=0;
        row_offsets_sub1<=0;
        row_offsets_add1<=0;
    end
    else
    begin
      row_offsets<=cnt_row_delay*WI_CH;
      row_offsets_sub1<=cnt_row_sub1*WI_CH;
      row_offsets_add1<=cnt_row_add1*WI_CH;
    end
end

reg [9:0]CH_offsets;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        CH_offsets<=0;
    else
      CH_offsets<=WIDTH1*CH_NO;
end

reg [9:0]col_offsets;
reg [9:0]col_offsets2;
reg [9:0]col_offsets1;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
    begin
        col_offsets<=0;
        col_offsets2<=0;
        col_offsets1<=0;
    end
    else
    begin
      col_offsets<=cnt_col;
      col_offsets2<=col_offsets;
      col_offsets1<=col_offsets2;
    end
end

reg [23:0]CH_add_col;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        CH_add_col<=0;
    else
      CH_add_col<=col_offsets+CH_offsets;
end

reg [23:0]Centre_add;
reg [23:0]Centre_add_sub1;
reg [23:0]Centre_add_add1;

always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
    Centre_add<=0;
    Centre_add_sub1<=0;
    Centre_add_add1<=0;
end
else
begin
    Centre_add<=row_offsets+CH_add_col;
    Centre_add_sub1<=row_offsets_sub1+CH_add_col;
    Centre_add_add1<=row_offsets_add1+CH_add_col;
end
end

reg [23:0]add;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
    add<=0;
else
case(data_4)
    8'h0:begin
                if((col_offsets1==10'd0)||(cnt_row_delay1==0))
                    add<=M;
                else
                    add<=Centre_add_sub1-1;
            end
    8'h1:begin
                if(cnt_row_delay1==10'd0)
                    add<=M;
                else
                    add<=Centre_add_sub1;
            end
    8'h2:begin
                if((cnt_row_delay1==0)||(col_offsets1==WIDTH))
                    add<=M;
                else
                    add<=Centre_add_sub1+1;
            end
    8'h3:begin
                if(col_offsets1==10'd0)
                    add<=M;
                else
                    add<=Centre_add-10'd1;
            end
    8'h4:begin
                    add<=Centre_add;
            end
    8'h5:begin
                if(col_offsets1==WIDTH)
                    add<=M;
                else
                    add<=Centre_add+10'd1;
            end
    8'h6:begin
                if((col_offsets1==10'd0)||(cnt_row_delay1==WIDTH))
                    add<=M;
                else
                    add<=Centre_add_add1-1;
            end
    8'h7:begin
                if(cnt_row_delay1==WIDTH)
                    add<=M;
                else
                    add<=Centre_add_add1;
            end
    8'h8:begin
                if((col_offsets1==WIDTH)||(cnt_row_delay1==WIDTH)) 
                    add<=M;
                else
                    add<=Centre_add_add1+1;
            end
default:add<=M;
endcase
end

reg [7:0]cnt_vs22;
always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt_vs22<=0;
else
    cnt_vs22<={cnt_vs22[6:0],cnt_vs2};
end

reg [7:0] data ;
always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    data <= 0 ;
else if(add==M) 
        data<=0;
else
    data <= data_buf[add] ;
end

 

reg cnt2_vs;
always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt2_vs<=0;
else if(cnt_2==0)
    cnt2_vs<=0;
else
    cnt2_vs<=1'b1;
end

reg [4:0]cnt2_vs1;
always @(posedge clk or negedge  rst_n)
begin
if(~rst_n)
    cnt2_vs1<=0;
else 
    cnt2_vs1<={cnt2_vs1[3:0],cnt2_vs};
end

 

wire [23:0]add_result;
wire result_vs;

juanji juanji_inst
(
    .clk(clk),
    .rst_n(rst_n),
    .data(data),
    .data_i(data_i1),
    .cnt2_vs(cnt2_vs1[4]),
    .add_result(add_result),
    .result_vs(result_vs)
);

parameter  wr_path_file = "E:/MATLAB/file/lei/data_output/v_dat_out.txt";
integer  fp_w ;
initial
begin 
    fp_w=$fopen(wr_path_file, "w");
end 

reg [23:0] data_out;
always @(posedge clk or negedge  rst_n)
begin 
if(~rst_n)
    data_out <= 0 ;
else if(!result_vs)
begin
    data_out <= add_result ;
    $fwrite(fp_w,"%x\n",data_out);
end
end

 

wire neg_close_vs;
assign neg_close_vs=(~cnt_vs22[6]&cnt_vs22[7]);

reg [10:0]neg_close_vs1;
always @(posedge clk or negedge  rst_n)
begin 
if(~rst_n)
    neg_close_vs1<=0;
else 
    neg_close_vs1<={neg_close_vs1[9:0],neg_close_vs};
end

 

always @(posedge clk )
begin 
if(neg_close_vs1[10])
     $fclose(fp_w);
end

endmodule

 

 

module juanji
(
    input clk,
    input rst_n,
    input [7:0]data,
    input [7:0]data_i,
    input cnt2_vs,
    output [23:0]add_result,
    output result_vs
);

reg cnt2_vs1,cnt2_vs2;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
    cnt2_vs1<=0;
    cnt2_vs2<=0;    
end
else
begin
  cnt2_vs1<=cnt2_vs;
  cnt2_vs2<=cnt2_vs1;
end
end

reg [7:0]data1;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
    data1<=0;
else
    data1<=data;
end

reg [7:0]data_i1;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
    data_i1<=0;
else
    data_i1<=data_i;
end

wire [15:0]result;

mult8_8    mult8_8_inst (
    .clock ( clk ),
    .dataa ( data1 ),
    .datab ( data_i1 ),
    .result (result )
    );
    
reg [23:0]add;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
    add<=0;
else if(!cnt2_vs2)
  add<=result;
else
  add<=add+result;
end

assign add_result=add;
assign result_vs=cnt2_vs2;
endmodule