STM32 - 定时器的设定 - 基础- 02 - Capture/compare channels 和相关设置寄存器 - 和STM32缩写词条解释

前言：捕捉比较通道：

STM32丰富的定时器的变化，就在这个模式，所以，复杂是必然的：当然，也可以简单来理解，就是通过选择定时器的输入的配置同时配置定时器的输出来获取我们需要的各种波形：

---

几个重要的缩写的意义：

CC: Capture compare

CCXE: Capture/Compare x output enable

CCXNE:Capture/Compare 1 complementary output enable

CCXNP:Capture/Compare x complementary output polarity

OPM:The one-pulse mode (OPM)

TI: Timer 

TIx: x Timer number，TIx Timer X，the timer channel inputs, TIx inputs.

IT: internal Trigger 

ITx：internal Trigger x

TI1FP1:Timer Input 1 Filtered Priority channel 1

ED: Edge Detector:

FDTS: Frequency of Division Timer Clock:The FDTS clock signal is derived from the timer clock signal, and the CKD[1:0] control bit-field sets the ratio between these two clock signals.

fCK_INT: Frequency clock of internal

fDTS = FDTS

TIxF_ED:TIx Edge Detector

ETRF：External Trigger input

Internal Trigger 0 (ITR0).

Internal Trigger 1 (ITR1).

Internal Trigger 2 (ITR2).

Internal Trigger 3 (ITR3).

TI1 Edge Detector (TI1F_ED)

Filtered Timer Input 1 (TI1FP1)

Filtered Timer Input 2 (TI2FP2)

External Trigger input (ETRF)

trigger signal (TRGI)

这里OC1M，是指output compare 1 通道模式：

OCxRef (active high).：output compared X channel Reference signal

trigger-out signal (TRGO)

---

CC 模式，看起来复杂，其实不然，也就是一大组配置的输入和一大组配置的比较，最后通过计数，极性，开关，事件控制，比较最后输出。

 

---

1 捕捉比较通道

1.1 输入阶段的详细说明

Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 78 to Figure 81 give an overview of one Capture/Compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be 1 used as trigger input by the slave mode controller or 2 as the capture command. It is prescaled before the capture register (ICxPS).

笔者案：上图是配置输入的一个原理图，这里我们看到从TIX的输入开始，或者通过fdts也就是系统的晶振等数字频率的输入，通过一个分频器（downcounter）,这个分倍率的选择通过（IC1F[3:0]: Input capture 1 filter）来控制，参考下面的寄存器的说明，我们发现分倍频的选择，通过乘法的计算可以为;2\4\8\2*6=12\2*8=16\4*6=32;分频后的信号给到TIxF；

TIXF 后面接的是一个带极性检测的边沿检测器，检测出上升沿、下降沿后往后输出为TIxFPx；

TIxFPx的输出，这里有一个开关电路，

而这个开关电路由：TIMx_CCER 的CCXP/CCXNP决定：（这里是CC1P/CC1NP）

这里决定TIxFPx的极性，

TIxFPx ：为定时器已经分频和极性选择后的信号：信号给到Capture/Compare 模式选择器TIMx_CCMR1

到这里，TIxFPx可以做为两个应用输入：

• used as trigger input by the slave mode

在主从模式下，通过CC1S的寄存器控制，CC1 channel,这里就是指Capture/Compare channel,可以配置为input，见下面CC1S的配置说明

• as the capture command.

这里信号有TIX变为ICX（input capture x）

通过再一次可选的分频器，ICxPS,然后到

TIMx_CCER 的CC1E，最后的输出使能，这样完整的

 

---

1.2 输入阶段按照输入顺序的寄存器详细说明

TIMx_CCMR1

I开头为输入模式设置，O开头为输出模式控制

IC1F[3:0]: Input capture 1 filter

TIMx_CCER

Bit 1 CC1P: Capture/Compare 1 output polarity

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity

Bit 0 CC1E: Capture/Compare 1 output enable

 

TIMx_CCMR1

CC1S:Capture/Compare 1 Selection

2 IC1PSC: Input capture 1 prescaler 

TIMx_CCER

 

Bit 0 CC1E: Capture/Compare 1 output enable

---

1.3 输出阶段的详细说明

The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain.

上一小节，输入阶段的最好输出为：ICxPS

首先，通过为输出模式控制器，

这里先设置输出的端口，OC1或者OC1N,

然后，TIMx_CCMR1，决定输出的模式，

然后，到刹车和死区控制，这块主要和电机控制相关，DTG[7:0]: Dead-time generator setup

这里控制死区的区间大小。

然后是，输入输出使能控制、极性控制

CCXE: Capture/Compare x output enable

CCXNE:Capture/Compare x complementary output Enable

CCXNP:Capture/Compare x complementary output polarity

然后又是死区控制相关的控制输出模块模块：

这里主要是MOE的关断控制，其他两个OSSI,OSSR,都是辅助控制关断的最好维持的电平。

---

ETRF可以作为模式控制的外部控制器，这一点在我的这篇文章里面有提到。

https://blog.csdn.net/yellow_hill/article/details/102207950

 

---

1.4 输出阶段按照输入顺序的寄存器详细说明

上图寄存器列表： 

TIMx_CCMR1 TIMx capture/compare mode register 1

Bit 7 OC1CE: Output compare 1 clear enable

0: OC1Ref is not affected by the ETRF （External Trigger input）input

1: OC1Ref is cleared as soon as a High level is detected on ETRF input

Bits 6:4 OC1M: Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived.

OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.(The polarity acts at the end of the chain.)

主要是比较：

 TIMx_CCR1 （捕捉比较寄存器的捕捉比较值）和 TIMx_CNT（定时器的计数值）的值，然后，针对比较结果做各种参考波形的输出。

000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.（这个用于定时器级联）

100: Force inactive level - OC1REF is forced low.

101: Force active level - OC1REF is forced high.

110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).

PWM的模式需要用到比较再输出。

111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive.

Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode.

TIM1 and TIM8 break and dead-time register (TIMx_BDTR)

Bits 7:0 DTG[7:0]: Dead-time generator setup

This bit-field defines the duration of the dead-time inserted between the complementary

outputs. DT correspond to this duration.

DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.

DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.

DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.

DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.

Example if TDTS=125ns (8MHz), dead-time possible values are:

0 to 15875 ns by 125 ns steps,

16 us to 31750 ns by 250 ns steps,

32 us to 63us by 1 us steps,

64 us to 126 us by 2 us steps

Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed

(LOCK bits in TIMx_BDTR register).

TIMx capture/compare enable register (TIMx_CCER)

 

Bit 0 CC1E: Capture/Compare 1 output enable

Bit 2 CC1NE: Capture/Compare 1 complementary output enable

0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.

1: On - OC1N signal is output on the corre

Bit 3 CC1NP: Capture/Compare 1 complementary output polarity

0: OC1N active high.

1: OC1N active low.

Bit 15 MOE: Main output enable

This bit is cleared asynchronously by hardware as soon as the break input is active. It is set

by software or automatically depending on the AOE bit. It is acting only on the channels

which are configured in output.

0: OC and OCN outputs are disabled or forced to idle state.

1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in

TIMx_CCER register).

See OC/OCN enable description for more details (Section 14.4.9: TIM1 and TIM8 capture/compare enable register (TIMx_CCER)).

Bit 11 OSSR: Off-state selection for Run mode

This bit is used when MOE=1 on channels having a complementary output which are

configured as outputs. OSSR is not implemented if no complementary output is implemented

in the timer.

See OC/OCN enable description for more details (Section 14.4.9: TIM1 and TIM8

capture/compare enable register (TIMx_CCER)).

0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).

1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1

or CCxNE=1. Then, OC/OCN enable output signal=1

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK

bits in TIMx_BDTR register).

Bit 10 OSSI: Off-state selection for Idle mode

This bit is used when MOE=0 on channels configured as outputs.

See OC/OCN enable description for more details (Section 14.4.9: TIM1 and TIM8

capture/compare enable register (TIMx_CCER)).

0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).

1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or

CCxNE=1. OC/OCN enable output signal=1)

Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK

bits in TIMx_BDTR register).