EDA--投票器电路设计 VHDL实现

问题描述

投票器电路设计

1）四个按键可为4人（甲乙丙丁）投票，每按下一次，票数加一

2）每2个数码管实时显示各人票数

3）设计计时按键（即投票开始），按下后投票计时开始，设置1分钟投票时间。时间到用LED灯显示，同时投票按键无效。

4）设计复位按键，按下后复位，票数清零。

5）投票结束后票数最多的数码管闪烁。

设计方案

• 四个投票按键–A、B、C、D

• 每两个数码管显示个人票数–动态扫描

• 设计计时按键和重置按键–set、reset

• 倒计时六十秒–分频

• 时间到LED灯亮，投票按键无效–给一个sign=0，时间到sign=1，控制投票按键无效

• 得票最多–通过累计投票按键被按下的次数

​ --通过将十位数字✖10加上个位

• 票数最多，数码管闪烁–动态扫描、分频

VHDL代码实现

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity vote4 is       --实体
	port (A,B,C,D,start:in std_logic;  
          reset:in std_logic;
          clk:in std_logic;
          sel:out std_logic_vector(7 downto 0);
          led:out std_logic:='0';
          led_num:out std_logic_vector(6 downto 0)
          );
end vote4;

architecture behave of vote4 is      --结构体
	signal choose_number:integer range 0 to 8:=0;
	signal choose_number1:integer range 0 to 3:=0;
	signal a1:integer range 0 to 9:=0;
	signal a2:integer range 0 to 9:=0;
	signal b1:integer range 0 to 9:=0;
	signal b2:integer range 0 to 9:=0;
	signal c1:integer range 0 to 9:=0;
	signal c2:integer range 0 to 9:=0;
	signal d1:integer range 0 to 9:=0;
	signal d2:integer range 0 to 9:=0;
	signal clk1:std_logic;   --1hz
	signal s60s:integer range 0 to 60:=0;	
	SIGNAL max:integer range 0 to 6:=0;
	signal xh:integer range 0 to 2:=0;
	signal sign:integer range 0 to 2:=0;

begin 
	process(clk)
	variable num:integer range 0 to 8 :=0;
	begin
		if clk'event and clk='1' then
			if num=7 then num:=0;
			else num:=num+1;
			end if;
		end if;
		choose_number<=num;
	end process;
	
	process(clk1)
	variable num:integer range 0 to 3 :=0;
	begin
		if clk1'event and clk1='1' then
			if num=2 then num:=0;
			else num:=num+1;
			end if;
		end if;
		choose_number1<=num;
	end process;
	
	process(choose_number,choose_number1,a1,a2,b1,b2,c1,c2,d1,d2,max)
	begin
	if xh=0 then
		case choose_number is
		--ABCD每两个数码管显示一个完整的数
			when 1 =>sel<="01111111";	--a
						case a1 is
							when 0 => led_num<="1111110";
							when 1 => led_num<="0110000";
							when 2 => led_num<="1101101";
							when 3 => led_num<="1111001";
							when 4 => led_num<="0110011";
							when 5 => led_num<="1011011";
							when 6 => led_num<="1011111";
							when 7 => led_num<="1110000";
							when 8 => led_num<="1111111";
							when 9 => led_num<="1111011";
							when others => led_num<="1111110";
						end case;
			when 2 =>sel<="10111111";case a2 is
							when 0 => led_num<="1111110";
							when 1 => led_num<="0110000";
							when 2 => led_num<="1101101";
							when 3 => led_num<="1111001";
							when 4 => led_num<="0110011";
							when 5 => led_num<="1011011";
							when 6 => led_num<="1011111";
							when 7 => led_num<="1110000";
							when 8 => led_num<="1111111";
							when 9 => led_num<="1111011";
							when others => led_num<="1111110";
						end case;
			when 3 =>sel<="11011111";	--b
							case b1 is
							when 0 => led_num<="1111110";
							when 1 => led_num<="0110000";
							when 2 => led_num<="1101101";
							when 3 => led_num<="1111001";
							when 4 => led_num<="0110011";
							when 5 => led_num<="1011011";
							when 6 => led_num<="1011111";
							when 7 => led_num<="1110000";
							when 8 => led_num<="1111111";
							when 9 => led_num<="1111011";
							when others => led_num<="1111110";
						end case;
			when 4 =>sel<="11101111";
							case b2 is
							when 0 => led_num<="1111110";
							when 1 => led_num<="0110000";
							when 2 => led_num<="1101101";
							when 3 => led_num<="1111001";
							when 4 => led_num<="0110011";
							when 5 => led_num<="1011011";
							when 6 => led_num<="1011111";
							when 7 => led_num<="1110000";
							when 8 => led_num<="1111111";
							when 9 => led_num<="1111011";
							when others => led_num<="1111110";
						end case;
			when 5 =>sel<="11110111";	--c
							case c1 is
							when 0 => led_num<="1111110";
							when 1 => led_num<