Verilog Modelsim仿真实验
Verilog Modelsim仿真实验打开Quartus II软件,点击File再点击New,选择Verilog FDL File,然后在空白处输入代码:module add4(S,COUT,CIN,X,Y);output COUT;output [3:0] S;input CIN;input [3:0]X,Y;reg [3:0] S;reg COUT;always @(X ,Y, CIN){COUT,S}=X+Y+CIN;endmodulemodule tb_41;w
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2021-05-07 22:37:31 ·
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