github上包含VIP的仓库

NAME	OWNER	STARS	URL	DESCRIPTION
tvip-axi	taichi-ishitani	47	https://github.com/taichi-ishitani/tvip-axi	AMBA AXI VIP
AHB2	GodelMachine	43	https://github.com/GodelMachine/AHB2	AMBA AHB 2.0 VIP in SystemVerilog UVM
riscv-vip	jerralph	29	https://github.com/jerralph/riscv-vip	For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
amiq_apb	amiq-consulting	26	https://github.com/amiq-consulting/amiq_apb	SystemVerilog VIP for AMBA APB protocol
amba3-vip	luuvish	19	https://github.com/luuvish/amba3-vip	amba3 apb/axi vip
AMBA_APB_SRAM	courageheart	16	https://github.com/courageheart/AMBA_APB_SRAM	AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
yuu_ahb	seabeam	7	https://github.com/seabeam/yuu_ahb	UVM AHB VIP
yuu_apb	seabeam	5	https://github.com/seabeam/yuu_apb	UVM APB VIP, part of AMBA3&AMBA4 feature supported
ahb2apb_bridge_vip	designsolver	4	https://github.com/designsolver/ahb2apb_bridge_vip	AHB to APB Bridge VIP
tvip-apb	taichi-ishitani	4	https://github.com/taichi-ishitani/tvip-apb	Verification IP for AMBA APB Protocol
yuu_vip_gen	seabeam	3	https://github.com/seabeam/yuu_vip_gen	UVM VIP architecture generator
axi4_vip	muneebullashariff	1	https://github.com/muneebullashariff/axi4_vip	Verification IP for APB protocol
i2c_vip	muneebullashariff	1	https://github.com/muneebullashariff/i2c_vip	Verification IP for I2C protocol
VIP	RuijieDV	1	https://github.com/RuijieDV/VIP	通用VIP
axi_vip	nsdeo12	1	https://github.com/nsdeo12/axi_vip	Axi VIP
apb_vip	asveske	1	https://github.com/asveske/apb_vip	APB VIP (UVM)
spi-vip	mcagriaksoy	1	https://github.com/mcagriaksoy/spi-vip	None
simple-spi-vip	mcagriaksoy	1	https://github.com/mcagriaksoy/simple-spi-vip	None
jtag_vip_uvm	emmanouil-komninos	1	https://github.com/emmanouil-komninos/jtag_vip_uvm	None
spi_vip	muneebullashariff	0	https://github.com/muneebullashariff/spi_vip	Verification IP for SPI protocol
apb_vip	muneebullashariff	0	https://github.com/muneebullashariff/apb_vip	Verification IP for APB protocol
git_i2c_master	davidchen6	0	https://github.com/davidchen6/git_i2c_master	i2c_master_vip
UART_VIP	kammulchandani	0	https://github.com/kammulchandani/UART_VIP	UART VIP Project
vip_clock	ottohorvath	0	https://github.com/ottohorvath/vip_clock	UVM based clock generator VIP
axi_vip	aunics	0	https://github.com/aunics/axi_vip	UVM SV based axi vip
SV_VIP	CelvinSXll	0	https://github.com/CelvinSXll/SV_VIP	SV VIP supported by UVM
vip_edaplaygrnd	emmanouil-komninos	0	https://github.com/emmanouil-komninos/vip_edaplaygrnd	None
dummy_vip	pulp-training	0	https://github.com/pulp-training/dummy_vip	Files for the IP Integration Exercise
tvip	taichi-ishitani	0	https://github.com/taichi-ishitani/tvip	None
RAM_VIP	NikolaF-95	0	https://github.com/NikolaF-95/RAM_VIP	UVM VIP for Single Port RAM Synchronous Read/Write
vip_reset	ottohorvath	0	https://github.com/ottohorvath/vip_reset	A simple basic reset VIP based on UVM 1.1d.
uart_vip	muneebullashariff	0	https://github.com/muneebullashariff/uart_vip	Verification IP for UART protocol
AxiVIP	nguyenquanicd	0	https://github.com/nguyenquanicd/AxiVIP	An AxiVIP supports both master and slave mode
FIFO_VIP	kammulchandani	0	https://github.com/kammulchandani/FIFO_VIP	None
uvm.vip	PhilOls	0	https://github.com/PhilOls/uvm.vip	None
axis_image_vip	hchsiao	0	https://github.com/hchsiao/axis_image_vip	None
spi_uvm_vip	me-sachinsingh	0	https://github.com/me-sachinsingh/spi_uvm_vip	None
spi_vip_uvm	Alexnorvag	0	https://github.com/Alexnorvag/spi_vip_uvm	None
APB3_SLAVE_VIP	ManojMJ5	0	https://github.com/ManojMJ5/APB3_SLAVE_VIP	None
1G-PCS-VIP	egorman44	0	https://github.com/egorman44/1G-PCS-VIP	UVM component that could be used in your Verification environment
AXI-VIP-Development	AniketBadhan	0	https://github.com/AniketBadhan/AXI-VIP-Development	None
APB_VIP_Repo	Dankumar	0	https://github.com/Dankumar/APB_VIP_Repo	None
AHB5	aunics	0	https://github.com/aunics/AHB5	AMBA AHB 5.0 VIP in SystemVerilog based on UVM
accessor_class_example	amiq-consulting	0	https://github.com/amiq-consulting/accessor_class_example	An example of using accessor classes and parameterization to reduce the number of VIP instances