一、前提:
1. rk3399核心板
2.uboot2017.09 源码
3. 多个MIPI显示屏的启动序列以及显示时序(重要)
4.rk3399MIPI通道0
二、内核中的dts,被修改部分,主要是显示部分
说明一下(uboot显示控制也是使用内核的dts来配置,所以只要关注内核的dts即可):
这里主要是分成三个部分:
1. mipi通道的一个整体设置,所有的屏都使用相同的配置。(显示正常)
2.panel-init-sequence,mipi屏的启动序列,发现每个屏都不相同,这里就多使用了几个不同的名字,以示区分。启动序列非常重要,没有配置或者配置错误将导致无法正常显示!!
3.display-timings中的各种时序,看上去是要根据屏的不同的屏而设置不同的时序。
&dsi {
status = "okay";
rockchip,lane-rate = <480>;
panel { //7inch
status = "okay";
compatible = "simple-panel-dsi";
reg = <0>;
power-supply = <&vcc3v3_sys>;
backlight = <&backlight>;
//enable-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
reset-delay-ms = <60>;
enable-delay-ms = <60>;
prepare-delay-ms = <60>;
unprepare-delay-ms = <60>;
disable-delay-ms = <60>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>;// |
// MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
#if 1 //7inch
panel-init-sequence-7inch = [ //主要是uboot要使用
39 00 03 F0 5A 5A
39 00 03 F1 5A 5A
39 00 03 FC A5 A5
39 00 03 D0 00 10
15 00 02 B1 12
39 00 05 B2 14 22 2F 04
15 00 02 B3 51
39 00 04 BC 01 4E 0A
39 00 06 E1 03 10 1C A0 10
39 00 09 EE 23 00 23 00 23 00 23 00
39 00 09 EF 34 12 98 BA 20 00 24 80
39 00 06 F2 02 08 08 40 10
39 00 0b F3 01 97 20 22 84 07 27 10 26 00
39 00 2e F4 02 02 1C 26 1D 02 03 03 03 1C 1C 03 00 0C 0C 03 02 03 06 06 13 14 01 15 01 04 02 61 78 79 72 E3 F3 F0 00 00 01 01 28 04 03 28 01 D1 32
39 00 1b F5 8C 3C 3C 5A 3B B7 4E 0F 33 23 02 59 54 52 45 46 60 02 60 80 27 26 52 25 7A 1F
39 00 07 F6 30 25 A6 00 00 00
39 00 21 F7 0E 0E 0A 0A 0F 0F 0B 0B 05 07 01 01 01 01 01 01 0C 0C 08 08 0D 0D 09 09 04 06 01 01 01 01 01 01
39 00 12 FA 00 30 0A 13 0B 11 17 16 19 21 23 22 23 22 21 20 26
39 00 12 FB 00 3A 0A 13 0B 11 17 16 19 23 27 28 29 28 29 28 30
15 00 02 B0 03
39 00 03 FD 23 09
39 00 07 FE 00 0D 03 21 80 78
39 32 04 C3 40 00 28
05 96 02 11 00
05 00 02 35 00
05 00 02 29 00
];
#endif //#if 1 7inch
//2022-12-09
panel-init-sequence-5inch-2 = [
39 00 04 FF 98 81 03
15 00 02 01 00
15 00 02 02 00
15 00 02 03 73
15 00 02 04 00
15 00 02 05 00
15 00 02 06 0A
15 00 02 07 00
15 00 02 08 00
15 00 02 09 01
15 00 02 0a 00
15 00 02 0b 00
15 00 02 0c 01
15 00 02 0d 00
15 00 02 0e 00
15 00 02 0f 1D
15 00 02 10 1D
15 00 02 11 00
15 00 02 12 00
15 00 02 13 00
15 00 02 14 00
15 00 02 15 00
15 00 02 16 00
15 00 02 17 00
15 00 02 18 00
15 00 02 19 00
15 00 02 1a 00
15 00 02 1b 00
15 00 02 1c 00
15 00 02 1d 00
15 00 02 1e 40
15 00 02 1f 80
15 00 02 20 06
15 00 02 21 02
15 00 02 22 00
15 00 02 23 00
15 00 02 24 00
15 00 02 25 00
15 00 02 26 00
15 00 02 27 00
15 00 02 28 33
15 00 02 29 03
15 00 02 2a 00
15 00 02 2b 00
15 00 02 2c 00
15 00 02 2d 00
15 00 02 2e 00
15 00 02 2f 00
15 00 02 30 00
15 00 02 31 00
15 00 02 32 00
15 00 02 33 00
15 00 02 34 04
15 00 02 35 00
15 00 02 36 00
15 00 02 37 00
15 00 02 38 3C
15 00 02 39 00
15 00 02 3a 40
15 00 02 3b 40
15 00 02 3c 00
15 00 02 3d 00
15 00 02 3e 00
15 00 02 3f 00
15 00 02 40 00
15 00 02 41 00
15 00 02 42 00
15 00 02 43 00
15 00 02 44 00
15 00 02 50 01
15 00 02 51 23
15 00 02 52 45
15 00 02 53 67
15 00 02 54 89
15 00 02 55 ab
15 00 02 56 01
15 00 02 57 23
15 00 02 58 45
15 00 02 59 67
15 00 02 5a 89
15 00 02 5b ab
15 00 02 5c cd
15 00 02 5d ef
15 00 02 5e 11
15 00 02 5f 01
15 00 02 60 00
15 00 02 61 15
15 00 02 62 14
15 00 02 63 0E
15 00 02 64 0F
15 00 02 65 0C
15 00 02 66 0D
15 00 02 67 06
15 00 02 68 02
15 00 02 69 07
15 00 02 6a 02
15 00 02 6b 02
15 00 02 6c 02
15 00 02 6d 02
15 00 02 6e 02
15 00 02 6f 02
15 00 02 70 02
15 00 02 71 02
15 00 02 72 02
15 00 02 73 02
15 00 02 74 02
15 00 02 75 01
15 00 02 76 00
15 00 02 77 14
15 00 02 78 15
15 00 02 79 0E
15 00 02 7a 0F
15 00 02 7b 0C
15 00 02 7c 0D
15 00 02 7d 06
15 00 02 7e 02
15 00 02 7f 07
15 00 02 80 02
15 00 02 81 02
15 00 02 82 02
15 00 02 83 02
15 00 02 84 02
15 00 02 85 02
15 00 02 86 02
15 00 02 87 02
15 00 02 88 02
15 00 02 89 02
15 00 02 8A 02
39 00 04 FF 98 81 04
15 00 02 38 01
15 00 02 39 00
15 00 02 6C 15
15 00 02 6E 2B
15 00 02 6F 33
15 00 02 8D 18
15 00 02 87 BA
15 00 02 26 76
15 00 02 B2 D1
15 00 02 B5 06
15 00 02 3A 24
15 00 02 35 1F
39 00 04 FF 98 81 01
15 00 02 22 0A
15 00 02 31 00
15 00 02 40 33
15 00 02 53 A8
15 00 02 55 a8
15 00 02 50 96
15 00 02 51 96
15 00 02 60 22
15 00 02 61 00
15 00 02 62 19
15 00 02 63 00
15 00 02 A0 08
15 00 02 A1 11
15 00 02 A2 19
15 00 02 A3 0D
15 00 02 A4 0D
15 00 02 A5 1E
15 00 02 A6 14
15 00 02 A7 17
15 00 02 A8 4F
15 00 02 A9 1A
15 00 02 AA 27
15 00 02 AB 49
15 00 02 AC 1A
15 00 02 AD 18
15 00 02 AE 4C
15 00 02 AF 22
15 00 02 B0 27
15 00 02 B1 4B
15 00 02 B2 60
15 00 02 B3 39
15 00 02 C0 08
15 00 02 C1 11
15 00 02 C2 19
15 00 02 C3 0D
15 00 02 C4 0D
15 00 02 C5 1E
15 00 02 C6 14
15 00 02 C7 17
15 00 02 C8 4F
15 00 02 C9 1A
15 00 02 CA 27
15 00 02 CB 49
15 00 02 CC 1A
15 00 02 CD 18
15 00 02 CE 4C
15 00 02 CF 33
15 00 02 D0 27
15 00 02 D1 4B
15 00 02 D2 60
15 00 02 D3 39
39 00 04 FF 98 81 00
15 00 02 36 00
15 00 02 35 00
05 ff 01 11
05 14 01 29
];
#if 1 //2022-12月取消使用
panel-init-sequence-5inch = [
39 00 04 FF 98 81 03
15 00 02 01 00
15 00 02 02 00
15 00 02 03 73
15 00 02 04 D3
15 00 02 05 00
15 00 02 06 0A
15 00 02 07 0E
15 00 02 08 00
15 00 02 09 01
15 00 02 0A 01
15 00 02 0B 01
15 00 02 0C 01
15 00 02 0D 01
15 00 02 0E 01
15 00 02 0F 01
15 00 02 10 01
15 00 02 11 00
15 00 02 12 00
15 00 02 13 00
15 00 02 14 00
15 00 02 15 00
15 00 02 16 00
15 00 02 17 00
15 00 02 18 00
15 00 02 19 00
15 00 02 1A 00
15 00 02 1B 00
15 00 02 1C 00
15 00 02 1D 00
15 00 02 1E 40
15 00 02 20 06
15 00 02 21 01
15 00 02 22 00
15 00 02 23 00
15 00 02 24 00
15 00 02 25 00
15 00 02 26 00
15 00 02 27 00
15 00 02 28 33
15 00 02 29 03
15 00 02 2A 00
15 00 02 2B 00
15 00 02 2C 00
15 00 02 2D 00
15 00 02 2E 00
15 00 02 2F 00
15 00 02 30 00
15 00 02 31 00
15 00 02 32 00
15 00 02 33 00
15 00 02 34 03
15 00 02 35 00
15 00 02 36 03
15 00 02 37 00
15 00 02 38 00
15 00 02 39 00
15 00 02 3A 40
15 00 02 3B 40
15 00 02 3C 00
15 00 02 3D 00
15 00 02 3E 00
15 00 02 3F 00
15 00 02 40 00
15 00 02 41 00
15 00 02 42 00
15 00 02 43 00
15 00 02 44 00
15 00 02 50 01
15 00 02 51 23
15 00 02 52 45
15 00 02 53 67
15 00 02 54 89
15 00 02 55 AB
15 00 02 56 01
15 00 02 57 23
15 00 02 58 45
15 00 02 59 67
15 00 02 5A 89
15 00 02 5B AB
15 00 02 5C CD
15 00 02 5D EF
15 00 02 5E 11
15 00 02 5F 08
15 00 02 60 02
15 00 02 61 00
15 00 02 62 01
15 00 02 63 0D
15 00 02 64 0C
15 00 02 65 02
15 00 02 66 02
15 00 02 67 02
15 00 02 68 02
15 00 02 69 02
15 00 02 6A 02
15 00 02 6B 0F
15 00 02 6C 02
15 00 02 6D 02
15 00 02 6E 02
15 00 02 6F 02
15 00 02 70 02
15 00 02 71 02
15 00 02 72 0E
15 00 02 73 06
15 00 02 74 07
15 00 02 75 08
15 00 02 76 02
15 00 02 77 00
15 00 02 78 01
15 00 02 79 0D
15 00 02 7A 0C
15 00 02 7B 02
15 00 02 7C 02
15 00 02 7D 02
15 00 02 7E 02
15 00 02 7F 02
15 00 02 80 02
15 00 02 81 0F
15 00 02 82 02
15 00 02 83 02
15 00 02 84 02
15 00 02 85 02
15 00 02 86 02
15 00 02 87 02
15 00 02 88 0E
15 00 02 89 06
15 00 02 8A 07
39 00 04 FF 98 81 04
15 00 02 6C 15
15 00 02 6E 1A
15 00 02 6F 33
15 00 02 8D 15
15 00 02 3A A4
15 00 02 87 2A
15 00 02 63 C0
15 00 02 26 76
15 00 02 B2 D1
39 00 04 FF 98 81 01
15 00 02 22 09
15 00 02 31 00
15 00 02 50 9E
15 00 02 51 9E
15 00 02 53 5D
15 00 02 55 61
15 00 02 60 14
15 00 02 A0 00
15 00 02 A1 1B
15 00 02 A2 2B
15 00 02 A3 15
15 00 02 A4 19
15 00 02 A5 2C
15 00 02 A6 20
15 00 02 A7 1D
15 00 02 A8 98
15 00 02 A9 1D
15 00 02 AA 29
15 00 02 AB 8A
15 00 02 AC 1D
15 00 02 AD 1C
15 00 02 AE 50
15 00 02 AF 24
15 00 02 B0 2C
15 00 02 B1 52
15 00 02 B2 60
15 00 02 B3 2A
15 00 02 C0 00
15 00 02 C1 1B
15 00 02 C2 2C
15 00 02 C3 16
15 00 02 C4 18
15 00 02 C5 2C
15 00 02 C6 20
15 00 02 C7 23
15 00 02 C8 98
15 00 02 C9 1D
15 00 02 CA 2A
15 00 02 CB 8A
15 00 02 CC 1E
15 00 02 CD 1D
15 00 02 CE 50
15 00 02 CF 24
15 00 02 D0 2C
15 00 02 D1 52
15 00 02 D2 60
15 00 02 D3 2A
39 00 04 FF 98 81 00
39 00 03 51 0F FF
15 00 02 53 24
15 00 02 55 01
15 00 02 35 00
05 00 01 34
15 0A 02 36 03
05 78 01 11
05 14 01 29
];
#endif //#if 1 //板2,有残影,2022-12月取消使用
disp_timings: display-timings {
native-mode = <&timing3>; //用于板1显示屏
native-mode-5inch = <&timing1>; //用于板2
native-mode-5inch-2 = <&timing2>;//用于板3
native-mode-7inch = <&timing0>; //用于板4
timing1: jc_5inch { //5inch
clock-frequency = <76600000>;
hactive = <720>;
hfront-porch = <80>;
hback-porch = <150>;
hsync-len = <10>;
vactive = <1280>;
vfront-porch = <20>;
vback-porch = <20>;
vsync-len = <10>;
hsync-active = <10>;
vsync-active = <10>;
de-active = <0>;
pixelclk-active = <0>;
};
timing0: timing0 { //7inch
clock-frequency = <62200000>;
hactive = <720>;
hfront-porch = <52>;
hback-porch = <52>;
hsync-len = <8>;
vactive = <1280>;
vfront-porch = <8>;
vback-porch = <5>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
timing2: jc_5inch-2 { //
clock-frequency = <76600000>;
hactive = <720>;
hfront-porch = <80>;
hback-porch = <150>;
hsync-len = <10>;
vactive = <1280>;
vfront-porch = <20>;
vback-porch = <20>;
vsync-len = <10>;
hsync-active = <10>;
vsync-active = <10>;
de-active = <0>;
pixelclk-active = <0>;
};
timing3: jiekou_jc { //序列为3
clock-frequency = <56480000>;
hactive = <1024>;
hfront-porch = <128>;
hsync-len = <32>;
hback-porch = <128>;
vactive = <600>;
vfront-porch = <16>;
vsync-len = <4>;
vback-porch = <16>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
三、uboot中涉及的显示源码部分
主要是两个文件:drivers/video/drm下,rockchip_panel.c和rockchip_display.c
3.1 rockchip_panel.c 中的修改部分(约在400行左右):
static int rockchip_panel_ofdata_to_platdata(struct udevice *dev)
{
struct rockchip_panel_plat *plat = dev_get_platdata(dev);
const void *data = NULL;
int len = 0;
int ret;com4_init();
com4_send_cmd();
mdelay(5);
//com4_recv_lcd_type_data();
ret = com4_recv_lcd_type_data();
if(ret == 6)
gd->lcd_type = 2; //表示 第二种5寸屏
else if(ret >= 0 && ret < 6)
{
gd->lcd_type = !(ret&1); //ret最低位为0表示7寸,ret最低位为1表示5寸,
}
else
gd->lcd_type = -1; //不能识别的屏
printf("com4_recv_data = %d\n",gd->lcd_type);plat->power_invert = dev_read_bool(dev, "power-invert");
plat->delay.prepare = dev_read_u32_default(dev, "prepare-delay-ms", 0);
plat->delay.unprepare = dev_read_u32_default(dev, "unprepare-delay-ms", 0);
plat->delay.enable = dev_read_u32_default(dev, "enable-delay-ms", 0);
plat->delay.disable = dev_read_u32_default(dev, "disable-delay-ms", 0);
plat->delay.init = dev_read_u32_default(dev, "init-delay-ms", 0);
plat->delay.reset = dev_read_u32_default(dev, "reset-delay-ms", 0);plat->bus_format = dev_read_u32_default(dev, "bus-format",
MEDIA_BUS_FMT_RBG888_1X24);
plat->bpc = dev_read_u32_default(dev, "bpc", 8);printf("gd->lcd_type = %d\n",gd->lcd_type);
if(gd->lcd_type >= 0)
{
if(gd->lcd_type == 2) // ,2022-12-09
{
data = dev_read_prop(dev, "panel-init-sequence-5inch-2", &len);
}
else
data = dev_read_prop(dev, gd->lcd_type?"panel-init-sequence-7inch":"panel-init-sequence-5inch", &len);
}
// else //不需要初始化序列!!! 2022-12-09
// data = dev_read_prop(dev, "panel-init-sequence", &len);// printf("data = %p\n",data);
if (data) {
plat->on_cmds = calloc(1, sizeof(*plat->on_cmds));
if (!plat->on_cmds)
return -ENOMEM;ret = rockchip_panel_parse_cmds(data, len, plat->on_cmds);
if (ret) {
printf("failed to parse panel init sequence\n");
goto free_on_cmds;
}
}data = dev_read_prop(dev, "panel-exit-sequence", &len);
if (data) {
plat->off_cmds = calloc(1, sizeof(*plat->off_cmds));
if (!plat->off_cmds) {
ret = -ENOMEM;
goto free_on_cmds;
}ret = rockchip_panel_parse_cmds(data, len, plat->off_cmds);
if (ret) {
printf("failed to parse panel exit sequence\n");
goto free_cmds;
}
}return 0;
free_cmds:
free(plat->off_cmds);
free_on_cmds:
free(plat->on_cmds);
return ret;
}
3.2 rockchip_display.c 中的修改部分 (约在267行)
static int display_get_timing_from_dts(struct panel_state *panel_state,
struct drm_display_mode *mode)
{
struct rockchip_panel *panel = panel_state->panel;
int phandle;
int hactive, vactive, pixelclock;
int hfront_porch, hback_porch, hsync_len;
int vfront_porch, vback_porch, vsync_len;
int val, flags = 0;
ofnode timing, native_mode;timing = dev_read_subnode(panel->dev, "display-timings");
if (!ofnode_valid(timing))
return -ENODEV;printf("111.gd->lcd_type = %d\n",gd->lcd_type);
native_mode = ofnode_find_subnode(timing, "timing");
if (!ofnode_valid(native_mode)) {
printf("gd->lcd_type = %d\n",gd->lcd_type);
if(gd->lcd_type >= 0)
{
if(gd->lcd_type == 2) // 第二块5寸屏
phandle = ofnode_read_u32_default(timing, "native-mode-5inch-2", -1); //2022-12-09
else
phandle = ofnode_read_u32_default(timing, gd->lcd_type?"native-mode-7inch":"native-mode-5inch", -1); //2022-12-05
}
else //默认为xx板的时序
phandle = ofnode_read_u32_default(timing, "native-mode", -1);
printf("phandle = %d\n",phandle);
native_mode = np_to_ofnode(of_find_node_by_phandle(phandle));
if (!ofnode_valid(native_mode)) {
printf("failed to get display timings from DT\n");
return -ENXIO;
}
}#define FDT_GET_INT(val, name) \
val = ofnode_read_s32_default(native_mode, name, -1); \
if (val < 0) { \
printf("Can't get %s\n", name); \
return -ENXIO; \
}#define FDT_GET_INT_DEFAULT(val, name, default) \
val = ofnode_read_s32_default(native_mode, name, default);FDT_GET_INT(hactive, "hactive");
FDT_GET_INT(vactive, "vactive");
FDT_GET_INT(pixelclock, "clock-frequency");
FDT_GET_INT(hsync_len, "hsync-len");
FDT_GET_INT(hfront_porch, "hfront-porch");
FDT_GET_INT(hback_porch, "hback-porch");
FDT_GET_INT(vsync_len, "vsync-len");
FDT_GET_INT(vfront_porch, "vfront-porch");
FDT_GET_INT(vback_porch, "vback-porch");
FDT_GET_INT(val, "hsync-active");
flags |= val ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
FDT_GET_INT(val, "vsync-active");
flags |= val ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
FDT_GET_INT(val, "pixelclk-active");
flags |= val ? DRM_MODE_FLAG_PPIXDATA : 0;FDT_GET_INT_DEFAULT(val, "screen-rotate", 0);
if (val == DRM_MODE_FLAG_XMIRROR) {
flags |= DRM_MODE_FLAG_XMIRROR;
} else if (val == DRM_MODE_FLAG_YMIRROR) {
flags |= DRM_MODE_FLAG_YMIRROR;
} else if (val == DRM_MODE_FLAG_XYMIRROR) {
flags |= DRM_MODE_FLAG_XMIRROR;
flags |= DRM_MODE_FLAG_YMIRROR;
}
mode->hdisplay = hactive;
mode->hsync_start = mode->hdisplay + hfront_porch;
mode->hsync_end = mode->hsync_start + hsync_len;
mode->htotal = mode->hsync_end + hback_porch;mode->vdisplay = vactive;
mode->vsync_start = mode->vdisplay + vfront_porch;
mode->vsync_end = mode->vsync_start + vsync_len;
mode->vtotal = mode->vsync_end + vback_porch;mode->clock = pixelclock / 1000;
mode->flags = flags;return 0;
}
四、发送自定义bootargs给内核,让内核的显示也能正常初始化。
下一节再讲内核中显示驱动的修改部分。
arch/arm/lib/bootm.c 文件:(约224行)
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
{
char *commandline = NULL;if(gd->lcd_type>=0)
{
char new_bootargs[512] = {0};
char* old_bootargs = env_get("bootargs");
int old_len = strlen(old_bootargs);strncpy(new_bootargs, old_bootargs, old_len);
sprintf(new_bootargs, "%s lcd_type=%d", new_bootargs, gd->lcd_type);
env_set("bootargs", new_bootargs);
}
commandline = env_get("bootargs");//char *commandline = env_get("bootargs");
if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
#ifdef CONFIG_OF_LIBFDT
debug("using: FDT\n");
if (image_setup_linux(images)) {
printf("FDT creation failed! hanging...");
hang();
}
#endif
} else if (BOOTM_ENABLE_TAGS) {
debug("using: ATAGS\n");
setup_start_tag(gd->bd);
if (BOOTM_ENABLE_SERIAL_TAG)
setup_serial_tag(¶ms);
if (BOOTM_ENABLE_CMDLINE_TAG)
setup_commandline_tag(gd->bd, commandline);
if (BOOTM_ENABLE_REVISION_TAG)
setup_revision_tag(¶ms);
if (BOOTM_ENABLE_MEMORY_TAGS)
setup_memory_tags(gd->bd);
if (BOOTM_ENABLE_INITRD_TAG) {
/*
* In boot_ramdisk_high(), it may relocate ramdisk to
* a specified location. And set images->initrd_start &
* images->initrd_end to relocated ramdisk's start/end
* addresses. So use them instead of images->rd_start &
* images->rd_end when possible.
*/
if (images->initrd_start && images->initrd_end) {
setup_initrd_tag(gd->bd, images->initrd_start,
images->initrd_end);
} else if (images->rd_start && images->rd_end) {
setup_initrd_tag(gd->bd, images->rd_start,
images->rd_end);
}
}
setup_board_tags(¶ms);
setup_end_tag(gd->bd);
} else {
printf("FDT and ATAGS support not compiled in - hanging\n");
hang();
}
}
谢谢观看,欢迎指教