日常工作实用同步FIFO（已Compile）

/***************************************************************
// File   : sync_fifo.v
// Auther : HoneyIC
// Time   : 2020.8.30
// Version: #1
// All rights reserved.
A synchronous fifo used in daily work, which is different from what we learned in the school.
The idea of this classification is very important, that is, separate coding of different modules.
What's more, please note that if-else in the sequential circuit is not written in full (eg. line 85). 
The advantage is that a gated control circuit can be generated, which can reduce the power consumption of the circuit.
"#1" can solve many timing problems in the synthesized circuit.
***************************************************************/

`timescale 1ns / 100ps

//`include "para.v"
//`define DLY 1

  
module sync_fifo #(
  parameter DEPTH = 'd24,
  parameter WIDTH = 'd8
)(
  // input
  clk,
  rst_n,
  wr,
  rd,
  data_in,  
  
  // output
  full,
  empty,
  overun,
  underun,
  data_out
);

  parameter DLY = 1;
  parameter RPT_WIDTH = DEPTH <= 'd2    ? 'd1 :
                        DEPTH <= 'd4    ? 'd2 :
                        DEPTH <= 'd8    ? 'd3 :
                        DEPTH <= 'd16   ? 'd4 :
                        DEPTH <= 'd32   ? 'd5 :
                        DEPTH <= 'd64   ? 'd6 :
                        DEPTH <= 'd128  ? 'd7 :
                        DEPTH <= 'd256  ? 'd8 :
                        DEPTH <= 'd512  ? 'd9 :
                        DEPTH <= 'd1024 ? 'd10: 'd11;
  // input
  input               clk;
  input               rst_n;
  input               wr;
  input               rd;
  input  [WIDTH-1:0]  data_in;
  
  // output
  output [WIDTH-1:0]  data_out;
  output              full;
  output              empty;
  output              overun;
  output              underun;
  
  // registers
  reg [    WIDTH-1:0] dataout;
  integer             i;
  reg [    DEPTH-1:0] fifo [WIDTH-1:0];
  reg [RPT_WIDTH-1:0] wptr;
  reg [RPT_WIDTH-1:0] rptr;
  reg [  RPT_WIDTH:0] gap_cnt;                           

  
  // 1. full, empty, overun, underun
  assign full    = (gap_cnt == DEPTH);
  assign empty   = (gap_cnt == 0);
  assign overun  = wr && (!rd) && full;
  assign underun = (!wr) && rd && empty;
  
  
  // 2. Updata gap_cnt
  // The advantage of this writing type is that it is easy to modify, especially in large projects. 
  assign gap_cnt_full = (gap_cnt == DEPTH);
  assign gap_cnt_add  = (wr && (!rd) && (!full));
  assign gap_cnt_sub  = ((!wr) && rd && (!empty));
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      gap_cnt <= #DLY 'd0;
    else if (gap_cnt_full)
      gap_cnt <= #DLY 'd0;
    else if (gap_cnt_add)
      gap_cnt <= #DLY gap_cnt + 1'b1;
    else if (gap_cnt_sub)
      gap_cnt <= #DLY gap_cnt - 1'b1;
    // The advantage of not writing 'else' here is that the Synthesis tool will generate gating clock.
    
  
  // 3. Updata wptr & rptr
  assign wptr_full = (wptr == (DEPTH - 1));
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      wptr <= 'd0;
    else if (wr)
      if (wptr_full)
        wptr <= #DLY 'd0;
      else
        wptr <= #DLY wptr + 1'b1;
  
  assign rptr_full = (rptr == (DEPTH - 1)); 
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      rptr <= #DLY 'd0;
    else if (rd)
      if (rptr_full)
        rptr <= #DLY 'd0;
      else
        rptr <= #DLY rptr + 1'b1;
  
  
  // 4. Write/Read data to/from fifo      
  always @(posedge clk or negedge rst_n)
    if (!rst_n)
      for (i=0; i<DEPTH; i=i+1)
        fifo[i] <= #DLY 'd0;
    else if (wr)
      fifo[wptr] <= #DLY data_in;
  
  assign data_out = fifo[rptr];


endmodule