AD7490介绍与使用
FEATURES，特性
- Fastthroughput rate: 1 MSPS，最大吞吐量
- Specified for VDD of 2.7 V to 5.25 V，指定电压范围
- Low power at maximum throughput rates，最大吞吐量低功率
- 5.4 mW maximum at 870 kSPS with 3 V supplies，功耗
- 12.5 mW maximum at 1 MSPS with 5 V supplies，功耗
- 16 (single-ended) inputs with sequencer，定序输入通道
- Wide input bandwidth，高带宽
- 69.5 dB SNR at 50 kHz input frequency，高灵敏
- Flexible power/serial clock speed management，可变的功耗/时钟速度管理
- No pipeline delays，无流水线延迟
- High speed serial interface,SPI/QSPI™/MICROWIRE™/，高速串行接口
- DSP compatible，dsp兼容
- Full shutdown mode: 0.5 µA maximum，完全关断电流
- 28-lead TSSOP and 32-lead LFCSP packages，封装
程序操作要点
- 使用CS和SCLK控制转换过程和数据采集，使设备能够容易地与微处理器或DSP进行接口。在CS的下降沿上采样输入信号，此时也开始转换。没有与零件相关的管路延迟。
- 通过设置控制寄存器中的相关位，模拟信号电压输入范围可以选择为0 V到RIFIN输入，或者选择0 V到2×RIFIN输入，转换结果具有直接二进制或两个互补输出编码。
- AD7490具有16个单端模拟输入，具有通道定序器，以允许按顺序编程的信道顺序转换。转换时间是由SCLK频率决定的，因为它也被用作主时钟来控制AD转换。
CONTROL REGISTER，控制寄存器
AD7490上的控制寄存器是一个12位的、只写寄存器。数据从ADC7490的DIN引脚加载，SCLK的下降沿读取一位。当寄存器数据在DIN线路上输入，同时转换结果在DOUT上输出。在DIN线路上传输的数据对应于下一个AD转换的配置。这需要16个串行时钟的每一个数据传输。只有在前12个下降时钟边缘上提供的信息（在CS下降沿之后）被加载到控制寄存器。
最低有效位（the least significant bit，lsb）， 最高有效位（the Most Significant Bit，msb），先发送最高有效位
表 5. Control Register，控制寄存器
| MSB | LSB | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| WRITE | SEQ | ADD3 | ADD2 | ADD1 | ADD0 | PM1 | PM0 | SHADOW | WEAK/TRI | RANGE |
表 6. Control Register Bit Functions控制寄存器
| Bit | Name | Description |
|---|---|---|
| 11 | WRITE写使能 | The value written to this bit of the control register determines whether the following 11 bits are loaded to the control register or not. If this bit is a 1, the following 11 bits are written to the control register可写; if it is a 0, the remaining 11 bits are not loaded to the control register, and it remains unchanged 不可写. |
| 10 | SEQ定序 | The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer function and access the Shadow register (see Table 9).SEQ和SHADOW联合使用 |
| 9 to 6 | ADD3 to ADD0通道地址 | These four address bits are loaded at the end of the present conversion sequence and select which analog input channel is to be converted on in the next serial transfer, or they may select the final channel in a consecutive sequence, as described in Table 9. The selected input channel is decoded as shown in Table 7. The next channel to be converted on is selected by the mux on the 14th SCLK falling edge. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data (see the Serial Interface section).通道序号 |
| 5, 4 | PM1, PM0电源管理 | Power management bits. These two bits decode the mode of operation of the AD7490, as shown in Table 8.电源管理，没啥要求就用1,1正常模式吧。 |
| 3 | SHADOW影子 | The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer function and access the Shadow register (see Table 9).通道定序 |
| 2 | WEAK/TRI输出状态 | This bit selects the state of the DOUT line at the end of the current serial transfer. If it is set to 1, the DOUT line is weakly driven to the ADD3 channel address bit of the ensuing conversion. If this bit is set to 0, DOUT returns to three-state at the end of the serial transfer. See the Control Register section for more details. DOUT空闲时的输出状态 |
| 1 | RANGE模拟输入范围 | This bit selects the analog input range to be used on the AD7490. If it is set to 0, the analog input range extends from 0 V to 2 × REFIN. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next conversion). For 0 V to 2 × REFIN, VDD = 4.75 V to 5.25 V. 采样范围 |
| 0 | CODING编码 | This bit selects the type of output coding used by the AD7490 for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion). AD转换结果的输出编码 |
表 7. Channel Selection通道选择
| ADD3 | ADD2 | ADD1 | ADD0 | Analog Input Channel |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | VIN0 |
| 0 | 0 | 0 | 1 | VIN1 |
| 0 | 0 | 1 | 0 | VIN2 |
| 0 | 0 | 1 | 1 | VIN3 |
| 0 | 1 | 0 | 0 | VIN4 |
| 0 | 1 | 0 | 1 | VIN5 |
| 0 | 1 | 1 | 0 | VIN6 |
| 0 | 1 | 1 | 1 | VIN7 |
| 1 | 0 | 0 | 0 | VIN8 |
| 1 | 0 | 0 | 1 | VIN9 |
| 1 | 0 | 1 | 0 | VIN10 |
| 1 | 0 | 1 | 1 | VIN11 |
| 1 | 1 | 0 | 0 | VIN12 |
| 1 | 1 | 0 | 1 | VIN13 |
| 1 | 1 | 1 | 0 | VIN14 |
| 1 | 1 | 1 | 1 | VIN15 |
表 8. Power Mode Selection电源管理
| PM1 | PM0 | Mode |
|---|---|---|
| 1 | 1 | Normal operation. In this mode, the AD7490 remains in full power mode, regardless of the status of any of the logic inputs.This mode allows the fastest possible throughput rate from the AD7490. 正常模式，不断电 |
| 1 | 0 | Full shutdown. In this mode, the AD7490 is in full shutdown mode, with all circuitry on the AD7490 powering down. The AD7490 retains the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed in the control register.全关断，最省电，停止工作 |
| 0 | 1 | Auto shutdown. In this mode, the AD7490 automatically enters shutdown mode at the end of each conversion when the control register is updated. Wake-up time from shutdown is 1 µs, and the user should ensure that 1 µs has elapsed before attempting to perform a valid conversion on the part in this mode.自动关断，至少关断1us |
| 0 | 0 | Auto standby. In this standby mode, portions of the AD7490 are powered down, but the on-chip bias generator remains powered up. This mode is similar to auto shutdown and allows the part to power up within one dummy cycle, that is, 1 µs with a 20 MHz SCLK.自动待机 |
Sequencer Operation定序操作
The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Table 9 outlines the four modes of operation of the sequencer.
表 9. Sequence Selection
| SEQ | SHADOW | Sequence Type |
|---|---|---|
| 0 | 0 | This configuration means the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits ADD0 through ADD3 in each prior write operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7490 selects the next channel for conversion (see Figure 12).不使用定序功能 |
| 0 | 1 | This configuration selects the Shadow register for programming. After the write to the control register, the following write operation loads the contents of the Shadow register. This programs the sequence of channels to be converted on continuously with each successive valid CS falling edge (see Shadow register, Table 10 and Figure 13). The channels selected need not be consecutive.按照shadow中设置的自定义定序转换 |
| 1 | 0 | If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the write operation. This allows other bits in the control register to be altered while in a sequence without terminating the cycle. 用来改变其他控制位，不打断当前的转换序列 |
| 1 | 1 | This configuration is used in conjunction with the ADD3 to ADD0 channel address bits to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel, as determined by the channel address bits in the control register (see Figure 14).从0开始到设定地址的顺序转换 |
图 12，单次 写/读
多通道ADC的正常运行，其中每次写入选择下一个要转换的通道。不使用定序功能。
reflects the normal operation of a multichannel ADC, where each serial transfer selects the next channel for conversion. In this mode of operation, the sequencer function is not used.
图 13，自定义序列 写/读
shows how to program the AD7490 to continuously convert on a particular sequence of channels using the Shadow register. To exit this mode of operation and revert back to the normal mode of operation of a multichannel ADC (as outlined in Figure 12), ensure that WRITE = 1 and SEQ = SHADOW = 0 on the next serial transfer.
图 14，从0开始的顺序 写/读
shows how a sequence of consecutive channels can be converted on without having to program the Shadow register or write to the part on each serial transfer. Again, to exit this mode of operation and revert back to the normal mode of operation of a multichannel ADC (as outlined in Figure 12), ensure that the WRITE = 1 and SEQ = SHADOW = 0 on the next serial transfer.
电源管理
Normal Mode (PM1 = PM0 = 1)正常模式，吞吐量最大
This mode is intended for the fastest throughput rate performance because the user does not have to worry about any power-up times with the AD7490 remaining fully powered at all times. Figure 22 shows the general diagram of the operation of the
AD7490 in this mode.
SERIAL INTERFACE串行接口，时序图
图 27 写控制寄存器同时读取数据
shows the detailed timing diagram for serial interfacing to the AD7490. The serial clock provides the conversion clock and also controls the transfer of information to and from the AD7490 during each conversion.
Cs下降沿开始
SCLK下降沿
读取：4位地址+12位数据
写入：12位参数+4位空数据
图 28，写影子寄存器
Writing information to the control register takes place on the first 12 falling edges of SCLK in a data transfer, assuming the MSB, that is, the WRITE bit, has been set to 1. If the control register is programmed to use the Shadow register, writing information to the Shadow register takes place on all 16 SCLK falling edges in the next serial transfer (see Figure 28). The Shadow register is updated upon the rising edge of CS, and the track-and-hold begins to track the first channel selected in the sequence.
ad7490.c
#include "spi1.h"
#include "ad7490.h"
#include "delay.h"
/* CSN片选 */
#define AD7490_CS_RCC RCC_AHB1Periph_GPIOB
#define AD7490_CS_PORT GPIOB
#define AD7490_CS1_PIN GPIO_Pin_6
#define AD7490_CS2_PIN GPIO_Pin_7
#define AD7490_CS1 PBout(6) //ad7490(1)的片选信号 : 1 enable , 0 disable
#define AD7490_CS2 PBout(7) //ad7490(2)的片选信号 : 1 enable , 0 disable
/* 片选 */
#define AD7490_CS1_EN() GPIO_ResetBits(AD7490_CS_PORT, AD7490_CS1_PIN)
#define AD7490_CS1_DIS() GPIO_SetBits(AD7490_CS_PORT, AD7490_CS1_PIN)
#define AD7490_CS2_EN() GPIO_ResetBits(AD7490_CS_PORT, AD7490_CS2_PIN)
#define AD7490_CS2_DIS() GPIO_SetBits(AD7490_CS_PORT, AD7490_CS2_PIN)
#define AD7490_CONV_CHANNEL AD_CONVERT_CHANNEL_SIZE
static uint16_t Adc_SampleBuffer[13];
struct t_ADC_SAMPLE_DATA g_ADC_Data;
void AD7490_Init(void)
{
SPI1_NSS_Init();
AD7490_CS1_DIS();
AD7490_CS2_DIS();
}
/*
*********************************************************************************************************
* 1100 0011 1111 0000 (0xC3F0)
* bit 11：控制写不写控制寄存器，write=1为装载
* bit 10&bit 3:实现排序功能及访问影子寄存器，seq=1 shadow=0 为不中断持续转换数据
* bit 9-6:最后一个转换通道0000
* bit 5-4:供电管理，PM1=PM0=1为正常模式，快速转换数据
* bit 2:DOUT引脚状态
* bit 1:电平范围，range=1为0-2VREF
* bit 0:config=1为二进制原码
*********************************************************************************************************
*/
#define AD7490_CTRL_REG_WRITE (1 << 11)
#define AD7490_CTRL_REG_SEQ (1 << 10)
#define AD7490_CTRL_REG_ADDR (15 << 6)
#define AD7490_CTRL_REG_PM (3 << 4)
#define AD7490_CTRL_REG_SHADOW (1 << 3)
#define AD7490_CTRL_REG_WEAK (1 << 2)
#define AD7490_CTRL_REG_RANGE (1 << 1)
#define AD7490_CTRL_REG_CODING (1 << 0)
void AD7490_ReadMultiChannel(u16 index, u16 *buffer, u16 total)
{
uint16_t k = 0, ctrl_reg = 0, temp_result = 0, temp_channel = 0, temp = 0, count = 0;
for(k = 0; k < 13; k++) //k为通道号
{
if(index)
AD7490_CS2_EN();
else
AD7490_CS1_EN();
if(k == 12)
{
ctrl_reg = 0x83; //控制寄存器一共12位，ctrl_reg为高八位，其中9-6位为对应的通道号
}
else
{
ctrl_reg = (0x8 | ((k & 0xc) >> 2)) * 16 + 0x3 | ((k & 0x3) << 2); //控制寄存器一共12位，ctrl_reg为高八位，其中9-6位为对应的通道号
}
temp = SPI1_ReadWriteByte(ctrl_reg * 256 + 0x10); //其实是16位数据
temp_result = temp & 0x0FFF; //传输16位数据流，0x10为低八位
temp_channel = (temp & 0xF000) >> 12;
if(k != 0)
{
if(temp_channel == (k - 1))
{
buffer[k - 1] = temp_result;
}
}
if(index)
AD7490_CS2_DIS();
else
AD7490_CS1_DIS();
ctrl_reg = 0;
}
}
void AD7490_Read(void)
{
uint16_t k = 0;
u16 *pbuf;
if(g_ADC_Data.list_head >= AD_DATA_LIST_SIZE)
g_ADC_Data.list_head = 0;
pbuf = g_ADC_Data.list[g_ADC_Data.list_head];
g_ADC_Data.list_new = g_ADC_Data.list_head;
g_ADC_Data.list_head++;
AD7490_ReadMultiChannel(0 , Adc_SampleBuffer, sizeof(Adc_SampleBuffer) / 2);
for(k = 0; k < 12; k++)
pbuf[k + 12] = Adc_SampleBuffer[11 - k];
AD7490_ReadMultiChannel(1, Adc_SampleBuffer, sizeof(Adc_SampleBuffer) / 2);
for(k = 0; k < 12; k++)
pbuf[k] = Adc_SampleBuffer[k];
}
ad7490.h
#ifndef __AD7490_H
#define __AD7490_H
#define AD_CONVERT_CHANNEL_SIZE 4
#define AD_DATA_LIST_SIZE 16
struct t_ADC_SAMPLE_DATA
{
u16 list[AD_DATA_LIST_SIZE][AD_CONVERT_CHANNEL_SIZE];
u16 list_head;
u16 list_new;
};
extern struct t_ADC_SAMPLE_DATA g_ADC_Data;
extern void AD7490_Init(void);
extern void AD7490_Read(void);
#endif 
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