如何让ISE综合时使用Block RAM?

本文介绍如何通过简单的Verilog代码实现RAM功能,并利用ISE工具将其综合为硬件中的Block RAM资源。文中提供了两个模块实例,展示了同步复位条件下RAM成功映射到Block RAM的过程,同时指出在异步复位情况下无法完成此映射。
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原文章地址:http://www.openhw.com/utoo/blog/10-03/185646_9119f.html

那天在OpenHW的论坛里闲逛,发现一个我以前也想过的问题:就是自己用代码来写RAM,然后让ISE把RAM综合成Block RAM?

   最近在解决使用ISE simulator 仿真divider报错问题时(还没解决,麻烦高手教我),发现了一个例程,就是在讲这个问题。

现在才发现原来这么简单,只是多加一句话

//
// The following example places 8-bit adders with
// constant in a single block RAM primitive
//

(* bram_map="yes" *)
module v_logic_bram_1 (clk, rst, A, B, RES);           

    input  clk, rst;                                       
    input  [3:0] A, B;                                     
    output [3:0] RES;                                     
    reg    [3:0] RES;                                        

    always @(posedge clk)                                 
    begin                                                 
        if (rst)                                              
            RES <= 4'b0000;                                        
        else                                                  
            RES <= A + B + 8'b0001;                                
    end                                                   

endmodule

综合后结果:

Device utilization summary:
---------------------------

Selected Device : 4vlx15sf363-12

 Number of Slices:                       0  out of   6144     0% 
 Number of IOs:                         14
 Number of bonded IOBs:                 14  out of    240     5% 
 Number of FIFO16/RAMB16s:               1  out of     48     2% 
    Number used as RAMB16s:              1
 Number of GCLKs:                        1  out of     32     3% 

 

但是也有要注意的地方,就是不能有异步复位信号,像这样:

 //
// In the following example, an asynchronous reset is used and
// so, the logic is not mapped onto block RAM
//

(* bram_map="yes" *)
module v_logic_bram_2 (clk, rst, A, B, RES);            

    input  clk, rst;                                         
    input  [3:0] A, B;                                       
    output [3:0] RES;                                       
    reg    [3:0] RES;
                                         
    always @(posedge clk or posedge rst)                    
    begin                                                   
        if (rst)                                                
            RES <= 4'b0000;                                         
        else                                                    
            RES <= A + B + 8'b0001;                                 
    end                                                     

endmodule   

综合结果:

Device utilization summary:
---------------------------

Selected Device : 4vlx15sf363-12

 Number of Slices:                       3  out of   6144     0% 
 Number of Slice Flip Flops:             4  out of  12288     0% 
 Number of 4 input LUTs:                 6  out of  12288     0% 
 Number of IOs:                         14
 Number of bonded IOBs:                 14  out of    240     5% 
    IOB Flip Flops:                      4
 Number of GCLKs:                        1  out of     32     3% 

 

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