看ISE 8.2i 的一点总结

最新推荐文章于 2020-06-12 18:20:20 发布

highhill520

最新推荐文章于 2020-06-12 18:20:20 发布

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分类专栏： xilinx_verilog设计文章标签： constraints tcl performance report user

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纯英文，看的偶剧痛苦。记下写关键部分。

the Tcl Console allows a user to enter Project Navigator specific Tcl commands

Design Summary
The Design Summary lists high-level information about your project, including overview
information, a device utilization summary, performance data gathered from the Place &
Route (PAR) report, constraints information, and summary information from all reports
with links to the individual reports.

ISE Simulator / Waveform Editor
ISE Simulator / Waveform Editor is a test bench and test fixture creation tool integrated in
the Project Navigator framework. Waveform Editor can be used to graphically enter
stimuli and the expected response, then generate a VHDL test bench or Verilog test fixture.
For details, refer to“Creating a Test Bench Waveform Using the Waveform Editor” in
Chapter 4.

Xilinx Synthesis Technology (XST)