FPGA 调试 Expecting digit in radix 2 错误

@E: CG353 :"C:\DLFIFOSLAVE\FIFOTest\source\FIFOTest.v":369:19:369:22|Expecting digit in radix 2

@E: CS187 :"C:\DLFIFOSLAVE\FIFOTest\source\FIFOTest.v":453:0:453:8|Expecting endmodule

今天写一个FPGA代码时，出现如上的错误 着了半天才发现问题，郁闷至极。

if(uart_status==16'h11)begin
delay <= delay+1'b'1;
if(delay ==4'h7) begin
uart_txd_data <= {std_rd_index_reg[15:0]};
std_sec_rst_reg <= 1'b1;
delay<=0;
uart_status <= 16'h12;
uart_txd_start <= 1'b1;
end
看到了吗？红色的字体出多了个'应该是1'b1。郁闷呀！