【开源】Linux内核修改cpuinfo描述信息

Jaeger1024

于 2024-10-11 20:04:34 发布

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文章标签： linux 开源嵌入式 risc-v

本文链接：https://blog.csdn.net/zxln007/article/details/142862085

版权

目的

需要在/proc/cpuinfo中增加相关字段

环境

RISC-V 荔枝派4A

修改

arch/riscv/kernel/cpu.c

static int c_show(struct seq_file *m, void *v)
{
	unsigned long cpu_id = (unsigned long)v - 1;
	struct device_node *node = of_get_cpu_node(cpu_id, NULL);
	const char *compat, *isa, *mmu;
	const char  *freq, *icache, *dcache, *l2cache, *tlb, *cacheline, *vecver;

	seq_printf(m, "processor\t: %lu\n", cpu_id);
	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
	// add vendor_id and model name
	seq_printf(m, "vendor_id\t: ZH\n");
	seq_printf(m, "model name\t: ZH T1 @2.0GHz\n");
	if (!of_property_read_string(node, "riscv,isa", &isa))
		print_isa(m, isa);
	if (!of_property_read_string(node, "mmu-type", &mmu))
		print_mmu(m, mmu);
	if (!of_property_read_string(node, "compatible", &compat)
	    && strcmp(compat, "riscv"))
		seq_printf(m, "uarch\t\t: %s\n", compat);

	if (!of_property_read_string(node, "cpu-freq", &freq))
		seq_printf(m, "cpu-freq\t: %s\n", freq);

	if (!of_property_read_string(node, "cpu-icache", &icache))
		seq_printf(m, "cpu-icache\t: %s\n", icache);

	if (!of_property_read_string(node, "cpu-dcache", &dcache))
		seq_printf(m, "cpu-dcache\t: %s\n", dcache);

	if (!of_property_read_string(node, "cpu-l2cache", &l2cache))
		seq_printf(m, "cpu-l2cache\t: %s\n", l2cache);

	if (!of_property_read_string(node, "cpu-tlb", &tlb))
		seq_printf(m, "cpu-tlb\t\t: %s\n", tlb);

	if (!of_property_read_string(node, "cpu-cacheline", &cacheline))
		seq_printf(m, "cpu-cacheline\t: %s\n", cacheline);

	if (!of_property_read_string(node, "cpu-vector", &vecver))
		seq_printf(m, "cpu-vector\t: %s\n", vecver);

	seq_puts(m, "\n");
	of_node_put(node);

	return 0;
}

主要增加的就两行

	// add vendor_id and model name
	seq_printf(m, "vendor_id\t: ZH\n");
	seq_printf(m, "model name\t: ZH T1 @2.0GHz\n");

修改完重新编译内核

cat /proc/cpuinfo

[root@openEuler ~]# cat /proc/cpuinfo
processor       : 0
hart            : 0
vendor_id       : ZH
model name      : ZH T1 @2.0GHz
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1

processor       : 1
hart            : 1
vendor_id       : ZH
model name      : ZH T1 @2.0GHz
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1

processor       : 2
hart            : 2
vendor_id       : ZH
model name      : ZH T1 @2.0GHz
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1

processor       : 3
hart            : 3
vendor_id       : ZH
model name      : ZH T1 @2.0GHz
isa             : rv64imafdcvsu
mmu             : sv39
cpu-freq        : 1.848Ghz
cpu-icache      : 64KB
cpu-dcache      : 64KB
cpu-l2cache     : 1MB
cpu-tlb         : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector      : 0.7.1