lpc1788_ucos\uCOSII_cpu\os_cpu.h cpu_c.c --ucosii移植在lpc1788--part4-part1

/*****************************************************************************************
*                                               uC/OS-II
*                                         The Real-Time Kernel
* File      : OS_CPU.H
* Version   : V2.86
* By        : Jean J. Labrosse
* For       : ARMv7M Cortex-M3
* Mode      : Thumb2
* Toolchain : RealView Development Suite
*             RealView Microcontroller Development Kit (MDK)
*             ARM Developer Suite (ADS)
*             Keil uVision
*****************************************************************************************/
#ifndef  OS_CPU_H
#define  OS_CPU_H
#ifdef   OS_CPU_GLOBALS
#define  OS_CPU_EXT
#else
#define  OS_CPU_EXT  extern
#endif
/*****************************************************************************************
*                                              DATA TYPES
*                                         (Compiler Specific)
*****************************************************************************************/
typedef unsigned char  BOOLEAN;
typedef unsigned char  INT8U;     /* Unsigned  8 bit quantity                           */
typedef signed   char  INT8S;     /* Signed    8 bit quantity                           */
typedef unsigned short INT16U;    /* Unsigned 16 bit quantity                           */
typedef signed   short INT16S;    /* Signed   16 bit quantity                           */
typedef unsigned int   INT32U;    /* Unsigned 32 bit quantity                           */
typedef signed   int   INT32S;    /* Signed   32 bit quantity                           */
typedef float          FP32;      /* Single precision floating point                    */
typedef double         FP64;      /* Double precision floating point                    */
typedef unsigned int   OS_STK;    /* Each stack entry is 32-bit wide                    */
typedef unsigned int   OS_CPU_SR; /* Define size of CPU status register (PSR = 32 bits) */
/*****************************************************************************************
*                                              Cortex-M1
*                                      Critical Section Management
* Method #1:  Disable/Enable interrupts using simple instructions.  After critical section, interrupts
*             will be enabled even if they were disabled before entering the critical section.
*             NOT IMPLEMENTED
*
* Method #2:  Disable/Enable interrupts by preserving the state of interrupts.  In other words, if
*             interrupts were disabled before entering the critical section, they will be disabled when
*             leaving the critical section.
*             NOT IMPLEMENTED
*
* Method #3:  Disable/Enable interrupts by preserving the state of interrupts.  Generally speaking you
*             would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
*             disable interrupts.  'cpu_sr' is allocated in all of uC/OS-II's functions that need to
*             disable interrupts.  You would restore the interrupt disable state by copying back 'cpu_sr'
*             into the CPU's status register.
*****************************************************************************************/
#define  OS_CRITICAL_METHOD   3
#if OS_CRITICAL_METHOD == 3
#define  OS_ENTER_CRITICAL()  {cpu_sr = OS_CPU_SR_Save();}          /* disable interrupt*/
#define  OS_EXIT_CRITICAL()   {OS_CPU_SR_Restore(cpu_sr);}          /* enable interrupt*/
#endif

/*****************************************************************************************
*                                        Cortex-M3 Miscellaneous
*****************************************************************************************/
#define  OS_STK_GROWTH        1       /* Stack grows from HIGH to LOW memory on ARM   */
#define  OS_TASK_SW()         OSCtxSw()

/*****************************************************************************************
*                                              PROTOTYPES
*****************************************************************************************/
#if OS_CRITICAL_METHOD == 3                       /* See OS_CPU_A.ASM     */
OS_CPU_SR  OS_CPU_SR_Save(void);
void       OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
#endif
void       OSCtxSw(void);
void       OSIntCtxSw(void);
void       OSStartHighRdy(void);
void       OS_CPU_PendSVHandler(void);
                                            /* See OS_CPU_C.C    */
void       OS_CPU_SysTickHandler(void);
void       OS_CPU_SysTickInit(void);
                                            /* See BSP.C         */
INT32U     OS_CPU_SysTickClkFreq(void);
#endif

/*****************************************************************************************
cpu_c.c
*****************************************************************************************/
#include "includes.h"
#define  CPU_INT_SRC_POS_MAX      ((((CPU_REG_NVIC_NVIC + 1) & 0x1F) * 32) + 1)
/*****************************************************************************************
*                                           CPU_IntSrcDis()
* Description : Disable an interrupt source.
* Argument(s) : pos     Position of interrupt vector in interrupt table :
*                           0       Invalid (see Note #1a).
*                           1       Invalid (see Note #1b).
*                           2       Non-maskable interrupt.
*                           3       Hard Fault.
*                           4       Memory Management.
*                           5       Bus Fault.
*                           6       Usage Fault.
*                           7-10    Reserved.
*                           11      SVCall
*                           12      Debug monitor.
*                           13      Reserved
*                           14      PendSV.
*                           15      SysTick.
*                           16+     External Interrupt.
* Return(s)   : none.
* Caller(s)   : Application.
* Note(s)     : (1) Several table positions do not contain interrupt sources :
*                   (a) Position 0 contains the stack pointer.
*                   (b) Positions 7-10, 13 are reserved.
*               (2) Several interrupts cannot be disabled/enabled :
*                   (a) Reset.
*                   (b) NMI.
*                   (c) Hard fault.
*                   (d) SVCall.
*                   (e) Debug monitor.
*                   (f) PendSV.
*
*               (3) The maximum Cortex-M3 table position is 256.  A particular Cortex-M3 may have fewer
*                   than 240 external exceptions and, consequently, fewer than 256 table positions.
*                   This function assumes that the specified table position is valid if the interrupt
*                   controller type register's INTLINESNUM field is large enough so that the position
*                   COULD be valid.
*****************************************************************************************/

void  CPU_IntSrcDis (CPU_INT08U  pos)
{
    #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
        CPU_SR      cpu_sr;
    #endif
    CPU_INT08U  group;
    CPU_INT08U  pos_max;
    CPU_INT08U  nbr;

    switch (pos)
    {
        case CPU_INT_STK_PTR:      /* ---------------- INVALID OR RESERVED --------------- */
        case CPU_INT_RSVD_07:
        case CPU_INT_RSVD_08:
        case CPU_INT_RSVD_09:
        case CPU_INT_RSVD_10:
        case CPU_INT_RSVD_13:
             break;
                                   /* ----------------- SYSTEM EXCEPTIONS ---------------- */
        case CPU_INT_RESET:        /* Reset (see Note #2).                                 */
        case CPU_INT_NMI:          /* Non-maskable interrupt (see Note #2).                */
        case CPU_INT_HFAULT:       /* Hard fault (see Note #2).                            */
        case CPU_INT_SVCALL:       /* SVCall (see Note #2).                                */
        case CPU_INT_DBGMON:       /* Debug monitor (see Note #2).                         */
        case CPU_INT_PENDSV:       /* PendSV (see Note #2).                                */
             break;

        case CPU_INT_MEM:          /* Memory management.                                   */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
             CPU_CRITICAL_EXIT();
             break;

        case CPU_INT_BUSFAULT:      /* Bus fault.                                           */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
             CPU_CRITICAL_EXIT();
             break;

        case CPU_INT_USAGEFAULT:    /* Usage fault.                                         */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
             CPU_CRITICAL_EXIT();
             break;

        case CPU_INT_SYSTICK:        /* SysTick.                                             */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_NXP_CTRL &= ~CPU_REG_NVIC_NXP_CTRL_ENABLE;
             CPU_CRITICAL_EXIT();
             break;
                                     /* ---------------- EXTERNAL INTERRUPT ---------------- */
        default:
            pos_max = CPU_INT_SRC_POS_MAX;
            if (pos < pos_max)
            {     /* See Note #3.                                         */
                 group = (pos - 16) / 32;
                 nbr   = (pos - 16) % 32;

                 CPU_CRITICAL_ENTER();
                 CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
                 CPU_CRITICAL_EXIT();
             }
             break;
    }
}

/*****************************************************************************************
*                                           CPU_IntSrcEn()
*
* Description : Enable an interrupt source.
*
* Argument(s) : pos     Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
*
* Return(s)   : none.
*
* Caller(s)   : Application.
*
* Note(s)     : (1) See 'CPU_IntSrcDis() Note #1'.
*               (2) See 'CPU_IntSrcDis() Note #2'.
*               (3) See 'CPU_IntSrcDis() Note #3'.
*****************************************************************************************/
void  CPU_IntSrcEn (CPU_INT08U  pos)
{
    #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
        CPU_SR      cpu_sr;
    #endif
    CPU_INT08U  group;
    CPU_INT08U  nbr;
    CPU_INT08U  pos_max;

    switch (pos)
    {
        case CPU_INT_STK_PTR:              /* ---------------- INVALID OR RESERVED --------------- */
        case CPU_INT_RSVD_07:
        case CPU_INT_RSVD_08:
        case CPU_INT_RSVD_09:
        case CPU_INT_RSVD_10:
        case CPU_INT_RSVD_13:
             break;
                                           /* ----------------- SYSTEM EXCEPTIONS ---------------- */
        case CPU_INT_RESET:                /* Reset (see Note #2).                                 */
        case CPU_INT_NMI:                  /* Non-maskable interrupt (see Note #2).                */
        case CPU_INT_HFAULT:               /* Hard fault (see Note #2).                            */
        case CPU_INT_SVCALL:               /* SVCall (see Note #2).                                */
        case CPU_INT_DBGMON:               /* Debug monitor (see Note #2).                         */
        case CPU_INT_PENDSV:               /* PendSV (see Note #2).                                */
             break;

        case CPU_INT_MEM:                  /* Memory management.                                   */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
             CPU_CRITICAL_EXIT();
             break;

        case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
             CPU_CRITICAL_EXIT();
             break;

        case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
             CPU_CRITICAL_EXIT();
             break;

        case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
             CPU_CRITICAL_ENTER();
             CPU_REG_NVIC_NXP_CTRL |= CPU_REG_NVIC_NXP_CTRL_ENABLE;
             CPU_CRITICAL_EXIT();
             break;
                                                                /* ---------------- EXTERNAL INTERRUPT ---------------- */
        default:
            pos_max = CPU_INT_SRC_POS_MAX;
            if (pos < pos_max) {                                /* See Note #3.                                         */
                 group = (pos - 16) / 32;
                 nbr   = (pos - 16) % 32;

                 CPU_CRITICAL_ENTER();
                 CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
                 CPU_CRITICAL_EXIT();
             }
             break;
    }
}