mc9s08lg32 时钟初始化

初始化MC9S08LG的时钟 fbus=1MHz

 

void MCU_Init(void)
{
   /***********Set up the clock registers to enter FEE mode *********************/
   
    //ICS Control Register 2 (ICSC2)//
    //
    //      bit 7     bit 6     bit 5     bit 4     bit 3   bit 2      bit 1     bit 0
    //    --------- --------- --------- --------- --------- ---------- --------- ---------
    //    |       BDIV        | RANGE   |   HGO   |   LP    |   EREFS  | ERCLKEN | EREFSTEN|
    //     ------------------- --------- --------- --------- ---------- --------- ---------
    //    |   0         0     |    0    |    0    |    0    |     1    |    1    |    0    |
    //     ------------------- --------- --------- --------- ---------- --------- --------
    //
    //
    //    BDIV     = 00    Set clock to divide by 1
    //    RANGE    = 0     Low Freq range selected (i.e. 32.768 kHz in high freq range)                     
    //    HGO      = 0     Ext Osc configured for low gain               
    //    LP       = 0     FLL is not disabled in bypass modes
    //    EREFS    = 1     Osc requested
    //    ERCLKEN  = 1     ICSERCLK active
    //    EREFSTEN = 0     Ext Reference clock is disabled in stop
    //
    ///*/
    
    /ICS Control Register 1 (ICSC1)///
    //
    //      bit 7     bit 6     bit 5     bit 4     bit 3   bit 2      bit 1     bit 0
    //     --------- --------- --------- --------- --------- ---------- --------- ---------
    //    |       CLKS        |            RDIV             |  IREFS   |IRCLKEN  |IREFSTEN |
    //     ------------------- --------- --------- --------- ---------- --------- ---------
    //    |   0         0     |    0    |    0    |    0    |     0    |    0    |    0    |
    //     ------------------- --------- --------- --------- ---------- --------- --------
    //
    //
    //    CLKS     = 00    Select clk source via FLL
    //    RDIV     = 000   Set to divide by 1 (i.e. 31.768kHz/1 = 31.768kHz - in range required by FLL)                     
    //    IREFS    = 0     Ext Ref clock selected
    //    IRCLKEN  = 0     ICSIRCLK inactive
    //    IREFSTEN = 0     Internal ref clock disabled in stop              
    //
    //
  //      bit 7     bit 6     bit 5     bit 4     bit 3   bit 2      bit 1     bit 0
    //     --------- --------- --------- --------- --------- ---------- --------- --------- 
    //        DRST            DMX32    IREFST          CLKST          OSCINIT  FTRIM1  
 //      ------------------- --------- --------- --------- ---------- --------- ---------
    //    |   0         0     |    0    |    0    |    0    |     0    |    0    |    0    |
    //     ------------------- --------- --------- --------- ---------- --------- --------
    //   DRST_DRS  00 Low range. 01 Mid range.
    //    DMX32      1 DCO is fined tuned for maximum frequency with 32.768 kHz reference.
  //    IREFST  0 Source of reference clock is external clock.
    //    CLKST    00 Output of FLL is selected.01 FLL Bypassed, Internal reference clock is selected  10 FLL Bypassed, External reference clock is selected.
   //     DRS  DMX32  Reference range  FLL factor  DCO range  
  //      00  0  31.25 - 39.0625 kHz  512  16 -20 MHz  
 //           1  32.768 kHz  608  19.92 MHz  
 //       01  0  31.25 - 39.0625 kHz  1024  32 -40 MHz  
 //           1  32.768 kHz  1216  39.85 MHz  
 //       10  0  31.25 - 39.0625 kHz  1536  48 -60 MHz  
 //           1  32.768 kHz  1824  59.77 MHz  
   ICSC2_BDIV      = 0X03;
   ICSC2_RANGE       = 0;   
   ICSC2_HGO         = 0;   //1
   ICSC2_EREFS       = 1;
   ICSC2_EREFSTEN    = 1;
   ICSC2_ERCLKEN     = 0;
  
   ICSSC_DMX32       = 0;
   ICSSC_DRST_DRS    = 0;
   ICSSC_IREFST      = 1;                 
  
   ICSSC_CLKST       = 0X01;             
  
   ICSC1_IRCLKEN     =0X01;       //1 ICSIRCLK active  The IREFS bit selects the reference clock source for the FLL.
   ICSC1_CLKS        = 0X00;     //01 Internal reference clock is selected.
   ICSC1_RDIV        = 0;       
   ICSC1_IREFS       = 1;      //1 Internal reference clock selected

 
  SCGC2_LCD=1;  //使能LCD时钟
 // SCGC1_RTC=1;  //使能RTC时钟
 // SCGC1_ADC=1;   //使能ADC时钟
 // SCGC1_TPM2=1;   //使能TPM2时钟
 // SCGC1_TPM1=1;   //使能TPM1时钟
 
 // SOPT1_COPE        = 0xc3;
    SOPT1_COPE        = 0x00;
     LCDC0_SOURCE=1; 
   }