test_signed_tbmodule test_signed(clk,data_out); parameter Data_OUT_WIDTH = 5; input clk; // output signed[Data_OUT_WIDTH - 1 : 0]data_out; output [Data_OUT_WIDTH - 1 : 0]data_out; assign data_out = -2; endmodule
module test_signed_tb; parameter Data_OUT_WIDTH = 5; reg clk; initial begin clk = 0; end always #10 clk = ~clk; wire [Data_OUT_WIDTH - 1 : 0] data_out; //wire [Data_OUT_WIDTH - 1 : 0] data_out; test_signed test_signed_inst(clk,data_out); reg signed [Data_OUT_WIDTH - 1 : 0] Temp_data_out = 0; always @(posedge clk) begin Temp_data_out <= data_out; end wire signed[15 : 0] result; wire signed[4:0] mux = 2; assign result = Temp_data_out * mux; endmodule