Verilog HDL 学习篇——快速同步FIFO

先入先出队列，主要用于暂存数据

module FAST_FIFO_MODULE
(
	input		wClock,	//时钟
	input		wReset,//复位
	input		wClear,//清除
	input		wWE,//写使能
	input		wRE,//读使能
	output		wFull,//满信号
	output		wEmtpy,//空信号
	input	[7:0]	wDataIn,//数据输入
	output	[7:0]	wDataOut//数据输出
);


reg [7:0] rMemery[0:3];//数组暂存的空间
reg [1:0] rWP,rRP;	//写指针和读指针寄存器
reg AlmostFull;//将要满标志

wire [1:0] wWP1,wRP1;//临时写读指针

assign wFull=(rWP==rRP)& AlmostFull;//判断是否满
assign wEmtpy=(rWP==rRP)&(!AlmostFull);//判断是否空

assign wDataOut=rMemery[rRP];
always @(posedge wClock or negedge wReset) 
	if(!wReset)begin//复位初始化
		rMemery[0]<=8'H00;
		rMemery[1]<=8'H00;
		rMemery[2]<=8'H00;
		rMemery[3]<=8'H00;
	end
	else if(wWE) rMemery[rWP]<=wDataIn;//如果要写入数据，则读取数据到暂存空间

assign wRP1=rRP+1'B1;
always @(posedge wClock or negedge wReset)
	if(!wReset) rRP<=2'B00;
	else if(wClear) rRP<=2'B00;
	else if(wRE) rRP<=wRP1;
	else if(AlmostFull && wWE) rRP<=wRP1;
	
	
assign wWP1=rWP+1'B1;
always @(posedge wClock or negedge wReset)
	if(!wReset) rWP<=2'B00;
	else if(wClear) rWP<=2'B00;
	else if(wWE) rWP<=wWP1;

always @(posedge wClock or negedge wReset)
	if(!wReset) AlmostFull<=1'B0;
	else if(wClear) AlmostFull<=1'B0;
	else if(wRE) AlmostFull<=1'B0;
	else if(wWE && (wWP1==rRP))AlmostFull<=1'B1;
endmodule